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san-
Visitor
Visitor
634 Views
Registered: ‎03-13-2018

AXI DMA S2MM issue

Hi,

We are trying to configure AXI DMA in zynq ultralscale+ (zcu111) board.

DMA is configured in simple mode with bus width of 256.

DMA S2MM path is not working.Tready signal  remains high and Interrupt of Completion (IOC ) is not generated.

Once S2MM reset is asserted Tready goes low for 4 cycles and then remains high.PL continiously provides data with valid whenever Tready is high.

With buswidth as 32 DMA S2mm path is working.

MM2S stream path Connection :

 - In MM2S path all signals are  taken separately and connected to custom IP block in PL.

S2MM stream path Connection :

 - In S2MM stream path all signals are made into "one external AXI Interface signal" and connected to AXI DMA S_AXIS_S2MM port.

 

AXI_DMA_Conf.jpgAXI_DMA.jpg

Suggestions would be helpful.

Regards,

sandeep

AXI_DMA_Conf.jpg
AXI_DMA.jpg
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2 Replies
johnmcd
Xilinx Employee
Xilinx Employee
523 Views
Registered: ‎02-01-2008

I've only used axi_dma SG. For s2mm completion, when configured as SG, a tlast signal needs to be generated. Otherwise the completion will never occur and an interrupt will not be generated.

For mm2s, the axi_dma will automatically create tlast.

I've attached an ipi module that I recently created and used for SG axi_dma. An axi_gpio is used to set when the tlast counter creates the tlast signal towards the s2mm dma port.

To use this module, add it as source to your vivado project, then in IPI right click and select 'add module'

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dgisselq
Scholar
Scholar
489 Views
Registered: ‎05-21-2015

@san-,

Did I read that right, that you were pulling reset active for one component of your bus but not for the whole bus?  If not, what did you mean by "once S2MM reset is asserted"?

Dan

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