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Contributor
Contributor
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Registered: ‎08-28-2020

AXI DMA SG mode not working

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I used the SG mode poll example given by xilinx to transfer data using Tx channel (MM2S channel of AXI DMA in SG mode). I studied the data transfer using ILA and did the following observations.

1. M_AXI_SG interface read the first buffer descriptor (which held at the address of 0x01000000)

M_AXI_SG read transactionM_AXI_SG read transaction

2. M_AXI_MM2S interface read data from an address (0xfbfa7951) which is different from the buffer address (0x01100000) relevant to the first buffer descriptor. 

M_AXI_MM2S ARADDRM_AXI_MM2S ARADDR

3. When R channel of M_AXI_MM2S reads RDATA, DECERR happens at RRESP of M_AXI_MM2S read channel.

M_AXI_MM2S ARADDR and RDATA with DECERRM_AXI_MM2S ARADDR and RDATA with DECERR

In the debug mode, after the transaction executed, I checked the SG mode register space and first buffer descriptor fields using XSCT as follows.

xsct% mrd 0x00000000a0000000 18 ===> SG REGISTER BASE
A0000000:   00010003
A0000004:   00010008
A0000008:   01000000
A000000C:   00000000
A0000010:   01000000 ===> SET TAIL DESCRIPTOR (SAME AS THE CURRENT DESCRIPTOR)
A0000014:   00000000
A0000018:   00000000
A000001C:   00000000
A0000020:   00000000
A0000024:   00000000
A0000028:   00000000
A000002C:   00000003
A0000030:   00010002
A0000034:   00010009
A0000038:   00000000
A000003C:   00000000
A0000040:   00000000
A0000044:   00000000
xsct% mrd 0x0000000001000000 16 ===> FIRST BUSSFER DESCRIPTOR
1000000: 01000040
1000004: 00000000
1000008: 01100000
100000C: 00000000
1000010: 00000000
1000014: 00000000
1000018: 0C00001E
100001C: 00000000
1000020: 00000000
1000024: 00000000
1000028: 00000000
100002C: 00000000
1000030: 00000000
1000034: 01100000
1000038: 00000000
100003C: 00000004

 

 Can anyone please explain what could be the possible issue for the Tx channel to receive data from a different address instead of the buffer address relevant to the first buffer descriptor ?

And I have another issue where I cannot identify why M_AXI_MM2S receives more than one packet even if I set SOF and EOF to the first buffer descriptor. Can anyone please explain that too ?

1 overall view.JPG

 

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Contributor
Contributor
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Registered: ‎08-28-2020

M_AXI_SG interface reads the buffer descriptor from the DRAM. Therefore address space relevant to the buffer descriptor needs to be flushed otherwise it will read junk values from the DRAM as given in the issue above.

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Moderator
Moderator
118 Views
Registered: ‎11-09-2015

Hi @kavinduvsomadas 

It would be interested to see the value read from the SG interface with the ILA. To sse if that matches with what you read on xsct


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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Contributor
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Registered: ‎08-28-2020

M_AXI_SG interface reads the buffer descriptor from the DRAM. Therefore address space relevant to the buffer descriptor needs to be flushed otherwise it will read junk values from the DRAM as given in the issue above.

View solution in original post