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Visitor
Visitor
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Registered: ‎07-30-2020

AXI DMA Simulation Error

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I am working on a AXI DMA (no scatter gather, separate read and write output ports) connected to a two input AXI Interconnect. In my simulation, I can get data to move through the AXI DMA without an issue. Input data to the AXI Interconnect is clean, and has been verified using AXI Protocol Checkers, but the output of the AXI Interconnect always shows X for wdata, wlast, and wstrb.

 
 
 
 

Is this to be expected? If not, if there anything I can add to help debug the problem?

 
 
 
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Visitor
Visitor
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Registered: ‎07-30-2020

Hi, thank you for responding.

I verified that the interconnect has at least 16 clocks for each reset. I found that the error was occurring with the crossbar within the AXI Interconnect. After more debug, I found the address mapping was incorrect (base and upper address). After this was corrected, the simulation will work as expected.

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Scholar
Scholar
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Registered: ‎05-21-2015

@xilinxuser1,

Did you give your design 16 clocks of !S_AXI_ARESETN?  Many Xilinx designs require a long reset.

Dan

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Visitor
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Registered: ‎07-30-2020

Hi, thank you for responding.

I verified that the interconnect has at least 16 clocks for each reset. I found that the error was occurring with the crossbar within the AXI Interconnect. After more debug, I found the address mapping was incorrect (base and upper address). After this was corrected, the simulation will work as expected.

View solution in original post

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