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Contributor
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Registered: ‎07-24-2018

AXI DMA Stall (Zynq Ultrascale+)

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I've set up a cyclic DMA transfer of around 64k bytes on the ZCU102. My DMA is connected to a MIG PL DDR module and is clocked at 300 MHz on MM2S and SG. The resulting data stream is fed into a FIFO which then feeds into a JESD204B TX core. 

 

My DAC output shows multiple stall periods that last for about 200-300 ns and the source seems to be the AXI DMA core. I've set up an ILA between the DMA and the FIFO which shows that MM2S_TVALID will go low for about 200-300ns at random intervals. I've attached corresponding screenshots of the DAC output and ILA waveform below. 

 

What could be causing TVALID to de-assert for such a long period of time? And during normal DMA operation, is TVALID supposed to be asserted continuously? 

 

 

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Contributor
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Registered: ‎07-24-2018

Re: AXI DMA Stall (Zynq Ultrascale+)

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It turns out the stall is due to bus contention between the scatter gather BDs and the data itself on PL DRAM.

I'd highly recommend moving both your BDs and the DMA data to block memory if it fits. This should eliminate your stalls.

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Contributor
Contributor
762 Views
Registered: ‎07-24-2018

Re: AXI DMA Stall (Zynq Ultrascale+)

Jump to solution

It turns out the stall is due to bus contention between the scatter gather BDs and the data itself on PL DRAM.

I'd highly recommend moving both your BDs and the DMA data to block memory if it fits. This should eliminate your stalls.

View solution in original post

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