11-06-2016 02:50 AM
I'm working on a project on the Zedboard where I have two AXI DMA's set up as follows.
1) Data is downloaded over TCP through Ethernet.
2) One DMA with TX sending roughly 80kb in cyclic mode to a FiFo.
3) The output from the FiFo is used to do some calculations on the data.
4) Which is then sent to a second FiFo. The output from that FiFo is connected to the RX of the other DMA.
5) The RX of the second DMA is setup in cyclic mode triggering interrupts roughly every 4.5 kb of incoming data.
6) The data is sent back over TCP through Ethernet.
Steps 1, 3, 4, 5 and 6 were all previously in place and have been working for some time now, without any problem. Step 2 was just recently changed, by
a) adding a new AXI DMA and changing the path from the old one to the new one, and
b) changing the old TX setup from non-cyclic to cyclic mode.
All of this was seemingly properly set up and it worked on my Zedboard, passing all the tests and all data was correct. However, when my coworker tried this out on his Zedboard only steps 1, 2, 3, 4 and 6 worked (wrong behavior 1). We could see in Vivado that all the ILA's triggered and that the data was correct throughout the system. However, No RX interrupts were triggered, which lead to only empty data sent back in step 6.
So we tried yet a different Zedboard and had a third outcome. On this Zedboard steps 1, 3, 4, 5 and 6 work correctly while step 2 only sent the data once, instead of repeatedly sending the data over and over (wrong behavior 2).
So far we have tried 6 different Zedboards (multiple time each) with the same three different outcomes, all from the same desktop, with the same binaries and the same data sent to the boards.
2 works as intended
2 has wrong behaviour 1
2 has wrong behaviour 2
Just to clarify, if I would name the Zeboards Zedboard A – Zedboard F
Zedboard A always has the same correct outcome, Zedboard B always has the same wrong outcome etc.
Both me and my coworker are running out of ideas on what could be going on here. Would highly appreciate any assistance on why different Zedboards with the same binaries can give 3 different outcomes.
11-15-2016 10:19 PM - edited 11-15-2016 10:20 PM
@aelvtsam One possibility is that your design has async paths (ie cdc signals) which are not being handled properly and it is behaving differently in different chips. Check your timing constraints, verify all synchronous paths are meeting timing and all asynchronous paths which are crossing clock domains are being managed according to proper digital design principles (multi-stage synchronization, async fifos etc).