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Adventurer
Adventurer
4,641 Views
Registered: ‎09-19-2016

AXI DMA in SG mode : Size of packets

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Hi guys!

 

Does anyone know how big our packets can be in hardware? Which hardware option affect our MAX_PACKET_LEN define in software? So basically, what is connection between hardware and this software define?

 

Thanks in advance!

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Xilinx Employee
Xilinx Employee
7,735 Views
Registered: ‎08-02-2011

Re: AXI DMA in SG mode : Size of packets

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The 'Width of Buffer Length Register' setting in the hardware configuration GUI limits the maximum value you can specify for a transfer length in a single BD.

www.xilinx.com

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Xilinx Employee
Xilinx Employee
7,736 Views
Registered: ‎08-02-2011

Re: AXI DMA in SG mode : Size of packets

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The 'Width of Buffer Length Register' setting in the hardware configuration GUI limits the maximum value you can specify for a transfer length in a single BD.

www.xilinx.com

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Adventurer
Adventurer
4,614 Views
Registered: ‎09-19-2016

Re: AXI DMA in SG mode : Size of packets

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That is something that I thought initially, but I got different idea when I saw this answer:

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Axi-DMA-correct-parameters/td-p/639576

 

According to this, Width of Buffer Length Register defines the maximum size of the entire transfer transaction... :/

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