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davidsummers
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Registered: ‎05-18-2015

AXI DMA only writing every other word

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I have a Zynq US+ design with two AXI-DMA cores operating in "stream to memory map mode".  One of them is working correctly.   The other one only writes every other 64 bit word.

Both AXI DMA cores are set up with 64 bit wide data on the stream side and 64 bit data on the MM side.  Both AXI DMA cores connect to an AXI Smartconnect block which connects to the S_AXI_HP0_FPD slave bus on the Zynq.  The HP0 bus is also set to 64 bits.

When I look at DDR4 in the Vitis Memory Monitor window, I see that the second AXI DMA writes every other 64 bit word (address 0, 0x10, 0x20, 0x30, etc.   The odd 64bit addresses are just garbage and never change.

 

I have tried setting the HP0 bus to 64 and 128 bits, setting the MM data width in the AXI DMA to Auto, 64, 128.   The result is always the same.

 

Any idea why the AXI DMA is skipping every other 64 bit word?

 

 

 

 

 

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davidsummers
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Registered: ‎05-18-2015

Update.  It looks like I was confused about a couple of points.  Both the DMA cores were actually acting the same way.  I got confused due to the caching of DDR.   Setting the HP0 bus to 128 bits and the AXI DMA core widths to "Auto" does work correctly.   If I set the width of the HP0 bus to 64, then I get the writes every other address.

 

It seems to be working correctly now.  Thanks!

 

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joancab
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Registered: ‎05-11-2015

DMA works independently of the bus width. You can move bytes on a 64-bit bus, and 32-bit words on an 8-bit bus. Data is just stored next to the previous.

I think you have an unintended width of 128 somewhere. If your 64-bit data is unexpectedly expanded to 128 then you introduce 64 bits of garbage. And I mean data width not bus width. Bus width is irrelevant (with regards of how data is stored), you don't need to fiddle with it.

 

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davidsummers
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Registered: ‎05-18-2015

Update.  It looks like I was confused about a couple of points.  Both the DMA cores were actually acting the same way.  I got confused due to the caching of DDR.   Setting the HP0 bus to 128 bits and the AXI DMA core widths to "Auto" does work correctly.   If I set the width of the HP0 bus to 64, then I get the writes every other address.

 

It seems to be working correctly now.  Thanks!

 

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