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barrygmoss
Contributor
Contributor
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Registered: ‎03-20-2018

AXI DMA sends data but doesn't complete transaction

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I have an AXI DMA core that I'm using for S2MM transfers in Direct Register mode. While simulating the design, I can get one DMA transaction through the core, but then it stalls.

 

When I check the S2MM DMA Status register after the transfer, I find that I get 0x00000000; i.e. the core is running, but it isn't IDLE. Also the S2MM Buffer Length is still showing the original value programmed. I've also enabled interrupts, but an interrupt on complete is never triggered.

 

I've checked and the AXIS stream properly terminates the end of transfer with TLAST asserted on the last beat of the transfer, coincident with TVALID and TREADY. This does indeed trigger the last words of input data to be sent out in an AXI4 frame with less than the maximum burst size.

 

All of this indicates that the DMA thinks that the transfer hasn't completed despite getting the TLAST signal in the incoming stream and sending out all the data over the AXI4 Master I/F.

 

My transfers are 56,816 bytes long (0xDDF0). I've tried programming this value directly to the S2MM Buffer Length register as well as a larger value like 0x80000. I've set the width of the buffer length register to 26 bits.

 

After the first transfer, I tried writing a new length value to the S2MM Buffer Length register (after writing a new target address to the DMA Destination Address Register), but the DMA IP won't accept more than a few more words of data before stalling, probably because it still thinks the previous transaction wasn't completed properly.

 

Any suggestions would be appreciated.

 

dma_config.png

 

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barrygmoss
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Registered: ‎03-20-2018

The problem was eventually found to be m_axi_s2mm_bvalid never getting asserted to acknowledge the AXI4 master address transaction. Once this was corrected, the DMA engine returned to the IDLE state following a DMA transaction. 

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demarco
Xilinx Employee
Xilinx Employee
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Registered: ‎10-04-2016

Hi @barrygmoss,

Do you have a waveform you can share? 

 

Other things you can check in your simulation:

1. Verify that AXI Reset is held low for at least 16 clock cycles.

2. Is the destination address aligned to a 16-byte boundary? If not, you need to enable unaligned transfers. 

3. When you set up the AXI DMA to perform the transfer, do you follow the programming sequence on page 69 of PG021?

 

https://www.xilinx.com/support/documentation/ip_documentation/axi_dma/v7_1/pg021_axi_dma.pdf#page=69

 

Regards,

 

Deanna

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barrygmoss
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Registered: ‎03-20-2018

Hi Deanna,

 

I can confirm that I am holding the AXI reset for longer than 16 cycles:

DMA Reset.png

 

Destination Addresses are 16-byte aligned: 

First transfer: 0x20000000

Second transfer: 0x20003000

 

My configuration sequence matches what's on page 69 or PG021:

Write 0x0000_7001 to S2MM_DMACR to enable the core and enable interrupts

 

Then for the first and subsequent transfers, I write the destination address to S2MM_DA_MSB and S2MM_DA_LSB, followed by the length of the transfer in bytes to S2MM_LENGTH.

 

 Here's an overview waveform of all the activity:

DMA Overview.png

 

Here's a close up of the initial configuration on the AXI-Lite Interface:

 

DMA Config.png

 

Here's a closer view of the period where the first data transfer occurs:

 

DMA Transfer Stall.png

 

Finally here's a closeup of the TLAST assertion

DMA TLAST Assertion.png

 

I've attempted to attach the waveform and config files, but I get a error messages:

The attachment's odmb_vfp_tb_behav.wdb content type (application/vnd.ms-works) does not match its file extension and has been removed.
The attachment's odmb_vfp_tb_behav.wcfg content type (application/octet-stream) does not match its file extension and has been removed.

 

Can you set up an EZMove for me to submit the full waveform file?

 

Regards,

Barry

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qhall
Explorer
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Registered: ‎10-24-2008

@barrygmoss@demarco  Hi Barry - thanks for creating this post and for your follow-up.  Deanna, would it make the most sense at this time for us to open an SR on this issue or is the information that Barry has provided to you sufficient to delve into this further.  Either way is fine, just let me know if you think an SR is the way to go.

 

--Quenton

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barrygmoss
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Registered: ‎03-20-2018

The problem was eventually found to be m_axi_s2mm_bvalid never getting asserted to acknowledge the AXI4 master address transaction. Once this was corrected, the DMA engine returned to the IDLE state following a DMA transaction. 

View solution in original post