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jonas.olofsson
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Registered: ‎02-28-2013

AXI Datamover 4.02a address increment problem

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I am doing a design with the AXI Datamover 4.02a and I am using it to move data from the DDR3 memory to a stream interface. But I have a problem regarding the address incrementations. If I try to transfer 65536 bytes (0x10000) the address to the DDR3 is repeated for every burst cycle. So I get the correct data during the first burst but the seconds burst gives the same data.

 

I have the following settings for the Datamover:

User tab:
C_INCLUDE_MM2S = 1

C_MM2S_BTT_USED = 23

C_MM2S_BURST_SIZE = 64

C_INCLUDE_S2MM = 0

 

System tab:

C_M_AXI_MM2S_DATA_WIDTH = 512
C_M_AXI_MM2S_TDATA_WIDTH = 512

 

Interconnect tab:

C_INTERCONNECT_M_AXI_MM2S_WRITE_ISSUING = 4
C_INTERCONNECT_M_AXI_MM2S_READ_ISSUING = 4

 

Running on the same AXI clk as the DDR3. The rest is set to default.

 

So what am I missing? Can I not use the datamover block to move this amount of data or? Any help would be appreciated. 

 

Regards
Jonas

 

 

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bwiec
Xilinx Employee
Xilinx Employee
8,991 Views
Registered: ‎08-02-2011

Please see AR54399.

 

This isn't very clear in the documentation, but you have to set bit 23 to 1 in the command word in order to get incremental bursts. The default is 'keyhole' or fixed-address type of bursts

www.xilinx.com

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bwiec
Xilinx Employee
Xilinx Employee
8,992 Views
Registered: ‎08-02-2011

Please see AR54399.

 

This isn't very clear in the documentation, but you have to set bit 23 to 1 in the command word in order to get incremental bursts. The default is 'keyhole' or fixed-address type of bursts

www.xilinx.com

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yzca
Adventurer
Adventurer
6,922 Views
Registered: ‎03-27-2009

hi Bweic,

 

is AR#54399 a typo? I am not able to find it on Xilinx website.

 

 

David C.

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bwiec
Xilinx Employee
Xilinx Employee
6,920 Views
Registered: ‎08-02-2011

Hi David,

 

No, it's not a typo, it's just not yet public :)

 

I posted it anyway for future reference in case anyone else ran into this problem and saw your post.

 

It should be public within a few days.

www.xilinx.com
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johnmcd
Xilinx Employee
Xilinx Employee
6,917 Views
Registered: ‎02-01-2008

Until the AR is released, set bit 23 of the cmd interface. New functionality was added in the datamover for keyhole accesses in v4 of the datamover but the doc wasn't updated.

 

Bit23 controls whether the address increments or not. cmd[23]=0 is keyhole, cmd[23]=1 is incrementing address.

paul_paul
Observer
Observer
5,349 Views
Registered: ‎09-06-2013
Topicstarter, please answer, was this information helpful for you or not? Because I have the same problem and I set the bit 23 to one, but the address to the DDR3 is still repeated for every burst cycle. So for me it doesn't help. Can anybody advice anything else?
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jonas.olofsson
Visitor
Visitor
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Registered: ‎02-28-2013

paul_paul, I'm sorry but I do not remember the exact solution to my question. What I do rember is that the AR linked helped me solved the problem. 

 

I do not have acces to the design I was working on anylonger so cannot check my solution. Hope you can find the answear in the AR. Soory I can't be of anymore help.

siktap
Scholar
Scholar
5,340 Views
Registered: ‎06-14-2012

http://www.xilinx.com/support/answers/54399.htm

 

For your refernce

 

Regards

Sikta

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paul_paul
Observer
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Registered: ‎09-06-2013

@paul_paul wrote:
Because I have the same problem

Sorry, the problem was in my own mistake

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