we are using the AXI-EPC core on ZYNQ device to access an external peripheral. The EPC is configured in aynchronuos mode and it's using 28-bit address bus and 16-bit data bus.
Accessing the external device in 16-bit mode (e.g. by mean of Xil_Out16) works fine as long as the address is 4-byte aligned (@addr 0x00, 0x04 etc...) but it fails when the accesses are performed on 2-byte aligned (@addr 0x02, 0x06 etc...).. By "fail" I mean that the write transaction completes (no data abort handler kicks in) but the data are not properly written - e.g. writing 0xFFFF will result in writing 0x0000.
As far as we understood it seems to us that the write strobes of AXI bus are neglected by EPC core.
Looking at AXI External Peripheral Controller v2.0 user guide (PG127) a note comes up to us:
AXI4-Lite Interface Module Note:The AXI4-Lite write access register is updated by the 32-bit AXI Write Data (*_wdata) signal, and is not impacted by the AXI Write Data Strobe (*_wstrb) signal. For a Write access, both the AXI Write Address Valid (*_awvalid) and AXI Write Data Valid (*_wvalid) signals should be asserted together.
Is it true that EPC neglects the AXI write strobes? It seems really strange to us that EPC is done that... Most likely something fishy is happening.
Thanks in advance for your support,
PS Note that we already enabled the data width matching feature of EPC. In that case the write succeeds but the access is actually doubled (likely done in 32-bit fashion).