I am using the Xilinx AXI 1G ethernet core connected to a Xilinx DMA block just like the ethernet example project. Using the Xilinx Linux driver I am able to boot petalinux and get an IP address. From there I can send and receive data just fine.
I need to process the data being received from the ethernet in the PL. I know that the Xilinx Linux ethernet driver depends on the ethernet AXI Stream ports (rxd and txd) being connected directly to the DMA block. Are there any patches available that can help me get around this requirement? Is there any way with the AXI 1G ethernet block that I can do any kind operation in the PL on the data received from the ethernet block?
Adding a block between the ethernet block and the DMA block results in the driver not working and the ethernet block not getting setup correctly. Currently the only option I see is processing the AXI Full data coming out of the DMA block. This will require conversion from AXI Full to AXI Stream.
This seems like a large capabilities oversight, unless I am really missing something. Any help with this would be greatly appreciated.
To process the rx (s2mm) stream from the Ethernet core in the PL, you can fork it, It will still go directly to the DMA, but can also go to your processing logic. If you want the data to go into a BRAM to process, you can use a Datamover core, but it needs to be set up to know where to put the data. If there is an issue with ready from your logic deasserting, you can insert an axis fifo just before your logic. I'm not sure how to deal with ready from the DMA deasserting as the fifo won't see that.