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jerry
Explorer
Explorer
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Registered: ‎04-16-2018

AXI-Full Master 64bit, MSB 32bit error

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I used "Create and Package New IP"-->"Create an AXI4 peripheral" created a M00_AXI 32bitMaster to access DDR through AXI HP1 FPD32bit),verified with nothing changed, read and write data correct.

2 questions:

1. First why "Create and Package New IP"-->"Create an AXI4 peripheral" only support 32bit, no other options?

2. I modified C_M00_AXI_DATA_WIDTH to 64bit, and AXI HP1 FPD to 64bit as well, then the result is bit31:0 is right while bit 63:32 wrong

I did modifications below:

1wire [C_TRANSACTIONS_NUM+2 : 0] burst_size_bytes;   change to:  wire [C_TRANSACTIONS_NUM+3 : 0] burst_size_bytes;

2assign M_AXI_WDATA = {axi_wdata[31:0]+1, axi_wdata[31:0]};

The waveform from ILA is:

1M_AXI_WDATA is right, i.e. 64'h00000019_00000018,  64'h0000001A_00000019...

2)once finished every burst, axi_awaddr + 128(was + 64 before

3M_AXI_RDATA is i.e. 64'h00000030_00000018, 64'h00000030_00000019,MSB 32bit is almost twice of LSB 32bit

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@jerry,

Looking over your design, I'm not seeing any problems with it.

I'm not sure why your design isn't working therefore.

Dan

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@jerry,

The AXI4 slave component built by clicking on "Create and package new IP" is quite broken.  I wouldn't use it, for this and other reasons.  (It's known for passing VIP testing, and then locking up in hardware.  It can't handle narrow AXI bursts, etc.).  You'll find this example to be protocol compliant, able to handle high throughput, and able to handle width expansion much easier.

Dan

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jerry
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Explorer
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Registered: ‎04-16-2018

Sorry, what I created is AXI4 master, NOT slave.

LSB 32bits is right, MSB 32bit is wrong.

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dgisselq
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Scholar
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Registered: ‎05-21-2015

@jerry,

How did you adjust WSTRB?

Dan

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jerry
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Explorer
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Registered: ‎04-16-2018

assign M_AXI_WSTRB = {(C_M_AXI_DATA_WIDTH/8){1'b1}};

I didn't adjust this driver, it's generated automatically, only configured C_M_AXI_DATA_WIDTH from 32 to 64.

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dgisselq
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Scholar
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Registered: ‎05-21-2015

@jerry,

A couple of thoughts: C_M_AXI_DATA_WIDTH is a parameter.  Is it getting overwritten by the context?  Or, again, Xilinx often generates their custom IP within wrappers.  One wrapper will often handle the protocol processing.  Is the C_M_AXI_DATA_WIDTH properly passed between the wrappers?

Barring those two, I'd need to see your custom IP in order to examine what's going on.

Dan

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jerry
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Explorer
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Registered: ‎04-16-2018

Many thanks for your idea! I checked C_M_AXI_DATA_WIDTH again, it's 64.

Below are the connection of myip to S_AXI_HP1_FPD, configuration of myip and myip zip.

2020-09-20_135820.png
2020-09-20_140657.png
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dgisselq
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Scholar
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Registered: ‎05-21-2015

@jerry,

Looking over your design, I'm not seeing any problems with it.

I'm not sure why your design isn't working therefore.

Dan

View solution in original post

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