cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
346 Views
Registered: ‎01-27-2020

AXI GPIO registers vs PS GPIO registers

Hi, I am new to Zynq architecture and a bit confused about the AXI. As my understanding Bank 0 and Bank 1 contain the 54 MIOs which can be configured and accessed via th PS GPIO registers.

Bank 2 and Bank 3 (AXI) contain the remaining 64 EMIOS. How do I configure and access the Bank 2 and Bank 3 GPIOs. 

AXI GPIO has a set of registers which is different from PS GPIO registers. Also the PS GPIO has DATA registers for Bank 2 and Bank 3? What is the purpose of these registers if we have a separate set of registers for AXI GPIOs?

Tags (4)
x_pl_gpio.PNG
x_ps_gpio.PNG
0 Kudos
2 Replies
Highlighted
Moderator
Moderator
235 Views
Registered: ‎04-09-2019

Hi,

You can use AXI GPIO IP in the PCW to use your GPIOs.

Regards,
Venu

0 Kudos
Highlighted
Xilinx Employee
Xilinx Employee
165 Views
Registered: ‎07-12-2018

Hi @vinaykumar.vadakoppu 

 

Bank 0, Bank 1, Bank 2 and Bank 3 have the GPIO signals coming from PS to peripherals and to PL. AXI GPIO is with the AXI interface and does not comes under the above Banks. So AXI GPIOs has separate registers.

Best Regards
Abhinay PS
------------------------------------------------------------------------------------------------------------------------------
Kindly note- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give kudos to a post which you think is helpful and reply oriented.
-------------------------------------------------------------------------------------------------------------------------------

0 Kudos