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Registered: ‎09-25-2007

AXI IIC Master Register Address?

Does the Xilinx AXI IIC IP support reading from I2C slaves that have internal I2C register maps? For example, I am interfacing to multiple video encoder/decoder chips which require the I2C master to specify an internal register address _after_ sending the device slave address in order to specify which internal register to read.

The datasheet for the encoder/decoders specifies a high-level I2C protocol for register reads as follows (acknowledge bits not included for sake of brevity):

  1. Start bit (sent by I2C master)
  2. 7-bit device slave address + R/W bit (Byte 1, sent by I2C master)
  3. 8-bit slave Internal Register Address (Byte 2, sent by I2C master)
  4. Register data (Bytes 3-N, sent by I2C slave)
  5. Stop bit (sent by I2C master)

Additionally, the I2C master may _not_ send a stop bit at any point between steps 2-4, or the slave device will return to the IDLE state and the sequence must be started over.

From reading the Xilinx AXI IIC IP product guide it would seem that for I2C reads the only method supported is (very high-level):

  1. User writes device slave address and r/w bit to TX_FIFO
  2. User writes the number (N) of bytes to be received (read) from slave device
  3. Xilinx AXI IIC core sends start bit, device_address + r/w bit
  4. Xilinx AXI IIC core waits for N bytes from slave
  5. Xilinx AXI IIC core sends stop bit

I don't see any way to get the Xilinx AXI IIC to function in a way that will work for my video encoder/decoders. Is it possible?

-- Jonathon
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Registered: ‎04-09-2019

Re: AXI IIC Master Register Address?


It supports for all kind of slave devices. Kinldy send me if you have any particular logs.




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