04-05-2018 09:19 AM
I am trying to change the SCL frequency of AXI_IIC 2.0 IP block by adjusting the timing registers (offset 0x128 - 0x144) however the SCL frequency is not changing. I read these registers before and after the I2C access to ensure they did not get reset by some other means. The values do not change from what I expect them to be. Yet the SCL frequency never changes from what the Vivado GUI setting is at build time. The bus itself works fine, no issues with general operation. It just seems the AXI_IIC IP is not honoring the timing registers.
I have been able to change AXI_IIC SCL frequency using this method on some of my older Zynq XC7Z010 designs.
Any advise / help much appreciated.
I am using single core Zynq XC7Z007S device with AXI_IIC IP in the PL.
Hardware is custom board running Linux 4.9.
Vivado toolchain is 2017.4