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oscargomezf
Visitor
Visitor
3,938 Views
Registered: ‎10-17-2016

AXI IIC V2.0: I2C Master Reading multiple bytes from I2C slave device.

Hi everyone,

I'm trying to use the AXI IIC Bus Interface v2.0. I need to configure the IIC AXI IP in master mode and I need to make a write of 2048 KBytes consecutively in an I2C Slave device and this works perfectly.

 

The problem is I need to make a read of 2048 KBytes consecutively ina an I2C slave device too, and this doesn't work. I only can write consecutively 255 Bytes, these are the steps I am following:

/* I2C Master device configuration */
*((u32 *)(XPAR_AXI_IIC_0_BASEADDR + XIIC_RESETR_OFFSET)) = 0x0A; /* Reset I2C */
WAIT(5);
*((u32 *)(XPAR_AXI_IIC_0_BASEADDR + XIIC_RFD_REG_OFFSET)) = 0x0F; /* Master: Number of bytes in Rx FIFO */
*((u32 *)(XPAR_AXI_IIC_0_BASEADDR + XIIC_CR_REG_OFFSET)) = XIIC_CR_TX_FIFO_RESET_MASK; /* Reset Tx FIFO */
*((u32 *)(XPAR_AXI_IIC_0_BASEADDR + XIIC_CR_REG_OFFSET)) = XIIC_CR_ENABLE_DEVICE_MASK; /* Enable I2C */

/* Send start bit + slave address for read */
*((u32 *)(XPAR_AXI_IIC_0_BASEADDR + XIIC_DTR_REG_OFFSET)) = (0x101 | (((*I2C_CONFIG & 0x00FF0000) >> 16) << 1));
*((u32 *)(XPAR_AXI_IIC_0_BASEADDR + XIIC_DTR_REG_OFFSET)) = 255;

while ( ! I2C_RX_EMPTY)
{
DATA[i++]= (u8)(*((u32 *)(XPAR_AXI_IIC_0_BASEADDR + XIIC_DRR_REG_OFFSET)));
}



But when I finish to read the 255 bytes, What I have to do in order to continue reading without generating a NACK and a new start condition on the I2C bus?

 

It seems to be that when the I2C Master device finishes of reading the 255 bytes it generates one NACK and a STOP condicion, and I need to tell the I2C Master that he has to read more bytes before generating one NACK and a STOP condicion, but I don't know how to manage this issue.

 

Any suggestion?

 

Best regards.

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8 Replies
painkil
Observer
Observer
3,124 Views
Registered: ‎09-27-2014

Hi, I'm having same situation. So, I want to know if you have cleared this issue.

 

Thank you.

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jawbone_101
Adventurer
Adventurer
2,687 Views
Registered: ‎05-07-2008

This thread is a little old but has been an issue for quite some time. I too am facing this issue.

Really someone from Xilinx would address these issues.

 

Regards

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pvenugo
Moderator
Moderator
2,650 Views
Registered: ‎07-31-2012

Hi,

 

AXI i2c-xiic driver have an i2c reading length limitation 255.

We have a change request to increase the size of read length.

 

Regards

Praveen


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jawbone_101
Adventurer
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2,627 Views
Registered: ‎05-07-2008

Hi Praveen,

Thank you for the response. Do you have any dates for when this may be implemented or any bets code for this fix. It is causing a lot of problems for our design.

 

Regards

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jawbone_101
Adventurer
Adventurer
2,626 Views
Registered: ‎05-07-2008

typo - I meant to say beta code

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jawbone_101
Adventurer
Adventurer
2,495 Views
Registered: ‎05-07-2008

@pvenugo

Hello, has any progress been made on this?

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pvenugo
Moderator
Moderator
2,328 Views
Registered: ‎07-31-2012

Hi @jawbone_101,

 

Not yet. The CR is under investigation to produce a patch.

 

Regards

Praveen


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jawbone_101
Adventurer
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868 Views
Registered: ‎05-07-2008

This thread is old - but it seems the driver developers are _finally_ trying to address the read length issue of more then 255 bytes.

There are comments in the commits about going into standard mode for reads > 255. There is a comment about repeated start is not happening in dynamic mode.

Can someone clarify this? Are you saying that if I do a read of more than 255 then you will not do a repeated start read?

 

 

 

Raviteja Narayanam
This is done because it is observed that
repeated start operation is not happening in dynamic mode read as
expected in a message set request from user space.

 

https://github.com/Xilinx/linux-xlnx/commit/9d348a7169a2bfb94fb3f22927171586a298f91f#diff-96c6776bffd044f013ae4283cddee850

https://github.com/Xilinx/linux-xlnx/commit/e1633c5626bf24e9bdedd0ed9d3d6297dc47bca4#diff-96c6776bffd044f013ae4283cddee850

 

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