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raj
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Registered: ‎05-24-2020

AXI IIC issue on ZCU102

Hello,

Board - ZCU102

I have followed https://forums.xilinx.com/t5/Design-and-Debug-Techniques-Blog/PS-IIC-and-AXI-IIC-debug-techniques/ba-p/1135303  and tried the simple c code attached there https://forums.xilinx.com/xlnx/attachments/xlnx/support_blog/197/2/i2c_simple_code.c . 

The c code is - 

 

u32 i;
u8 pl_mst_read[255];

xil_printf("\n--------PL MAS INIT------\n");
//Master settings
Xil_Out32(0x8000C100, 0x1) ;
delay(5000000000);
Xil_Out32(0x8000C120, 0xF) ;
delay(5000000000);

//Read operation to read from slave @0x48
Xil_Out32(0x8000C108, 0x148) ; // Slave address + Write
delay(5000000000);
Xil_Out32(0x8000C108, 0x08B) ; // Sub-register address of the slave
delay(5000000000);
Xil_Out32(0x8000C108, 0x149) ; // Slave address + Read
delay(5000000000);
Xil_Out32(0x8000C108, 0x201) ; // Read 1 byte from Sub-register address of the slave
delay(5000000000);


for (i = 0 ; i< 1;i++) {
while(((Xil_In32(0x8000C104))&(0x40))); // Check for RX_FIFO not empty to read data from RX_FIFO
delay(5000000000);
pl_mst_read[i] = Xil_In32(0x8000C10C); // Read data from RX FIFO
delay(5000000000);
}
for (i = 0 ; i< 1;i++)
xil_printf("mst rec 0x%0x\n\r", pl_mst_read[i]);

 

 

 

image.png

 
 

image.png

 

 

set_property -dict {PACKAGE_PIN AD1 IOSTANDARD LVCMOS18 PULLUP true} [get_ports rf_eeprom_scl_io]
set_property -dict {PACKAGE_PIN AD2 IOSTANDARD LVCMOS18 PULLUP true} [get_ports rf_eeprom_sda_io]

 

 
The program gets stuck while checking for RX FIFO not empty. 

The contents of the registers when the program gets stuck are below - 


0x8000C100: 0x00000009 
0x8000C104: 0x00000040 
0x8000C108: 0x0000008B 
0x8000C10C: 0x00000000 
0x8000C110: 0x00000000 
0x8000C114: 0x00000002 
0x8000C118: 0x00000000 
0x8000C11C: 0x00000000 
0x8000C120: 0x0000000F 
0x8000C124: 0x00000000 

Is modification in the C code or the AXI IIC configuration required ?

@venui 

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venui
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Registered: ‎04-09-2019

Hi,

Please check the slave address and modify the source code accordingly.

Regards,

Venu

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raj
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Registered: ‎05-24-2020

@venui Thank you for the suggestion. I changed the slave address to 0xA0 and executed the C code. The program gets stuck while checking for RX FIFO not empty. This is the modified sequence -

Xil_Out32(0x8000C108, 0x1A0) ; // Slave address + Write
delay(5000000000);
Xil_Out32(0x8000C108, 0x08B) ; // Sub-register address of the slave
delay(5000000000);
Xil_Out32(0x8000C108, 0x1A1) ; // Slave address + Read
delay(5000000000);
Xil_Out32(0x8000C108, 0x201) ; // Read 1 byte from Sub-register address of the slave
delay(5000000000);

This is the eeprom chip being communicated with https://www.mouser.com/datasheet/2/268/24AA256UID-256K-I2C-Serial-EEPROM-with-EUI48-EUI64-1358324.pdf . 

Voltage - 1.8V
IIC freq - 100KHz
AXI freq - 100MHz

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venui
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Registered: ‎04-09-2019

Hi Raj, The slave device address is correct but you have to write register address to be write/read to be 16-bit not 8-bit that is the problem. 

 

Xil_Out32(0x8000C108, 0x1A0) ; // Slave address + Write
delay(5000000000);
Xil_Out32(0x8000C108, 0x000) ; // Sub-register address of the slave higher byte
Xil_Out32(0x8000C108, 0x000) ; // Sub-register address of the slave lower byte
delay(5000000000);
Xil_Out32(0x8000C108, 0x1A1) ; // Slave address + Read
delay(5000000000);
Xil_Out32(0x8000C108, 0x201) ; // Read 1 byte from Sub-register address of the slave
delay(5000000000);

Regards,

Venu 

raj
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Registered: ‎05-24-2020

@venui Thank you for the suggestion. I tried reading EUI-48bit address from the eeprom chip. (page 13 of the eeprom datasheet https://www.mouser.com/datasheet/2/268/24AA256UID-256K-I2C-Serial-EEPROM-with-EUI48-EUI64-1358324.pdf )

Xil_Out32(0x8000C108, 0x1A0);

Xil_Out32(0x8000C108, 0x07F);

Xil_Out32(0x8000C108, 0x07A);

Xil_Out32(0x8000C108, 0x1A1);

Xil_Out32(0x8000C108, 0x206); //read 6 bytes

The program gets stuck checking for RX_FIFO empty after reading first byte. The registers values are below - 


0x8000C100:  0x00000001 
0x8000C104:  0x00000048 
0x8000C108:  0x00000006 
0x8000C10C: 0x00000080 

I have enabled Data FIFO (512 deep packet mode) inside AXI interconnect. We're using AXI4Lite

Found a similar unresolved issue here https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/AXI-IIC-Multi-Byte-Read/m-p/1089982 

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venui
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Registered: ‎04-09-2019

Hi @raj can you please monitor the I/O status and post it here so that i can understand what is going on with bus.

Regards,

Venu

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raj
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Registered: ‎05-24-2020

@venui 

This is chipscope data when the program gets stuck whle checking for RX_FIFO empty after reading the first byte 

After reading first byteAfter reading first byte

 

Chipscope trigger at TX_FIFO write 0x206. First byte 0x80 is read 

image.png

I followed this post https://forums.xilinx.com/t5/Embedded-Linux/AXI-IIC-2-0-xps-iic-2-00-Randomly-Stops-Hangs/m-p/766975  and set  SCL inertial delay to 300ns and SDA inertial delay to 50ns. Also, I connected the interrupt to Zynq processor.

 

UPDATE - I changed the code  (added delays in between commands)

 

 

Xil_Out32(0x8000C040, 0xA); //reset iic core

u32  i;
u8  pl_mst_read[255];
		  	  //Master settings
Xil_Out32(0x8000C100, 0x3) ; //reset TX_FIFO
delay(500000);
Xil_Out32(0x8000C100, 0x1) ; //enable IIC
delay(500000);
Xil_Out32(0x8000C120, 0xF) ; //read fifo buffer size
delay(500000);
        //Read operation to read from slave @0xA0
Xil_Out32(0x8000C108, 0x1A0) ;   // Slave address + Write
delay(50000000);
Xil_Out32(0x8000C108, 0x07F) ;   // Sub-register address of the slave
delay(500000000);
Xil_Out32(0x8000C108, 0x07A) ;   // Slave address + Read
delay(500000000);
Xil_Out32(0x8000C108, 0x1A1) ;   //read access
delay(500000000000);
Xil_Out32(0x8000C108, 0x206) ;   // Read 6 byte from Sub-register address of //the slave
delay(500000000000);


for (i = 0 ; i< 6;i++) {
  delay(500000000000);
  while((Xil_In32(0x8000C104))&(0x40));  // Check for RX_FIFO not empty to read data from RX_FIFO
	delay(500000000000);
	pl_mst_read[i] = Xil_In32(0x8000C10C);  // Read data from RX FIFO
	usleep(15);
	delay(500000000000);
}

for (i = 0 ; i< 6;i++){
	xil_printf("mst rec 0x%0x\n\r", pl_mst_read[i]);
}

 

 



After running 15-20 times, the program kept getting stuck at RX_FIFO empty after reading first byte but 1 time it read all 6 bytes. Output is below -


 mst rec 0x80
 mst rec 0x1F
 mst rec 0x12
 mst rec 0xD9
 mst rec 0xBC
 mst rec 0x94

I ran the program again to reproduce the output but it kept getting stuck after reading first byte. What might be the issue? Looks like the AXI IIC core operation is random and unpredictable while reading multiple bytes in repeated start mode. 

I have tried reading single byte at a time and it works without any issues. 

The test sequence is - 
1) Launch on Hardware (system debugger) (Reset APU, Reset RPU, Enable RPU split mode, Run psu_init, PL powerup)
2) Program excecutes and gets stuck. back to step 1

The program is a baremetal application running on RPU R0 

I haven't power cycled the FPGA during these tests. Can that help ? 

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raj
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Registered: ‎05-24-2020

@venui Do you have any suggestion ?

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