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skajiha1
Observer
Observer
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Registered: ‎12-08-2019

AXI INTERCONNECT RTL : Read data signal is indefinite

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Hello,

・ Vivado 2018.3
・ AXI Inter Connect RTL (1.7)
・ Simurator: Xcelium 19.11-a001

Library compiled with vivado([Tools] → [Compile Simulation Libraries])

・"xrun" option

-reflib "$ref_lib_dir/unisim:unisim" \
-reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
-reflib "$ref_lib_dir/secureip:secureip" \
-reflib "$ref_lib_dir/unimacro:unimacro" \
-reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
-reflib "$ref_lib_dir/xpm:xpm" \
-reflib "$ref_lib_dir/lib_pkg_v1_0_2:lib_pkg_v1_0_2" \
-reflib "$ref_lib_dir/fifo_generator_v13_2_3:fifo_generator_v13_2_3" \
-reflib "$ref_lib_dir/lib_fifo_v1_0_12:lib_fifo_v1_0_12" \
-reflib "$ref_lib_dir/blk_mem_gen_v8_4_2:blk_mem_gen_v8_4_2" \
-reflib "$ref_lib_dir/lib_bmg_v1_0_11:lib_bmg_v1_0_11" \
-reflib "$ref_lib_dir/axi_pcie_v2_9_0:axi_pcie_v2_9_0" \
-reflib "$ref_lib_dir/axi_interconnect_v1_7_15:axi_interconnect_v1_7_15" \
-reflib "$ref_lib_dir/xilinx_vip:xilinx_vip" \
-reflib "$ref_lib_dir/smartconnect_v1_0:smartconnect_v1_0" \
-reflib "$ref_lib_dir/axi_protocol_checker_v2_0_4:axi_protocol_checker_v2_0_4" \
-reflib "$ref_lib_dir/lib_cdc_v1_0_2:lib_cdc_v1_0_2" \
-reflib "$ref_lib_dir/proc_sys_reset_v5_0_13:proc_sys_reset_v5_0_13" \
 
-makelib xcelium_lib/xil_defaultlib \
  "../VIVADO/project_1/project_1.srcs/sources_1/ip/AXI_INTRCNCT_M/sim/AXI_INTRCNCT_M.v" \
-endlib
 
When simulating AXI INTERCONNECT RTL, the following ports will be "X".
-S00_AXI_RDATA [31: 0] = 32'hxxxxxxxx
-S00_AXI_RRESP [1: 0] = 2'hx
 
Not enough libraries?
or
Is the setting when generating the IP incorrect?
 
Global
  Component Name:AXI_INTRCNCT_M
  Number of Slave Interfaces:1
  Slave Interface Thread ID Width:0
  Master Interface ID Width:4
  Address Width:32
  Interconnect Internal Data Width:32
  Synchronization Stages across Asynchronous Clock Crossings:3
 
Interface
  Master Interface
    Data Width:64
    Async ACLK:check
    ACLK Ratio:none
    Arbiter Priority:-
    Reg Slice:No check
  Slave Interface 0
    Data Width:32
    Async ACLK:no check
    ACLK Ratio: 1:1
    Arbiter Priority:0
    Reg Slice:No check
 
Read Write Channels
  Master Interface
  AXI Channels:READ/WRITE
  Read Channels
    Acceptance:1
    FIFO Depth:0
    Packet FIFO:No Check
  Write Channels
    Acceptance:1
    FIFO Depth:0
    Packet FIFO:No Check
 
  Slave Interface 0
  AXI Channels:READ/WRITE
  Read Channels
    Acceptance:1
    FIFO Depth:0
    Packet FIFO:No Check
  Write Channels
    Acceptance:1
    FIFO Depth:0
    Packet FIFO:No Check
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skajiha1
Observer
Observer
309 Views
Registered: ‎12-08-2019

Hello,

Read access was confirmed. The following signals are enabled in read data channcel.

-S00_AXI_RDATA [31: 0] = 32'hxxxxxxxx
-S00_AXI_RRESP [1: 0] = 2'hx

View solution in original post

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skajiha1
Observer
Observer
310 Views
Registered: ‎12-08-2019

Hello,

Read access was confirmed. The following signals are enabled in read data channcel.

-S00_AXI_RDATA [31: 0] = 32'hxxxxxxxx
-S00_AXI_RRESP [1: 0] = 2'hx

View solution in original post

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