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943 Views
Registered: ‎03-25-2019

AXI Interconnect - Clock domains

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Hello

I have design in which the GPO AXI Master will run at 100MHZ, whereas most of my logic in PL will be at anywhere between 3 and 28 MHZ (derived from off-chip clock generator). Since much of the traffic is accessing status/control registers I can't use FIFO or Dual port RAM for the clock crossing.

I am intending using AXI Smart Interconnect to cross the clock domains.

Is there any potential problem with sourcing the slave side of this Smart Interconnection with a clock  that could change dynamically (although it will be glitch-free)?

Thank you.

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demarco
Xilinx Employee
Xilinx Employee
847 Views
Registered: ‎10-04-2016

Hi david.wende@ltts.com,

I had to ask the designers about this one. It should be okay to change clocks on the fly. There are a few things to consider:

1. Make sure that the flexible clock domain (the 3 to 28MHz one) is identified as being a different clock domain than the 100MHz domain. This forces the interconnect to infer an "async" clock crossing so appropriate logic is included. The clock domain is usually inferred from the AXI Interface connections you make, but you can verify the tools are making the correct inference by selecting the AXI i/f on the interconnect and reviewing its properties as shown below.smartconnAxiProperties.JPG

 

2. Avoid scaling the clock while traffic is in flight. 

Regards,

Deanna

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demarco
Xilinx Employee
Xilinx Employee
848 Views
Registered: ‎10-04-2016

Hi david.wende@ltts.com,

I had to ask the designers about this one. It should be okay to change clocks on the fly. There are a few things to consider:

1. Make sure that the flexible clock domain (the 3 to 28MHz one) is identified as being a different clock domain than the 100MHz domain. This forces the interconnect to infer an "async" clock crossing so appropriate logic is included. The clock domain is usually inferred from the AXI Interface connections you make, but you can verify the tools are making the correct inference by selecting the AXI i/f on the interconnect and reviewing its properties as shown below.smartconnAxiProperties.JPG

 

2. Avoid scaling the clock while traffic is in flight. 

Regards,

Deanna

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832 Views
Registered: ‎03-25-2019

Thanks for the good answer.

(System not letting me give KUDO.)

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garethc
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Registered: ‎06-29-2011

Hi david.wende@ltts.com 

To give "Kudos" select the Thumbs up icon and not the word Kudos.

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Kind regards,
Gareth
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