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hyungsoo1.kim
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Registered: ‎03-24-2019

AXI Intereconnector

Hi

I have question with AXI interconnecor Xilinx' IP

As a result of latency measure, AXI interconnector's latency dealy  is about 20 clk from input to output. I think it's too long 

Do anybody know how to optimize axi interconnector under 5clk or another axi interconnector which have short latency delay IP 

Thanks!

 

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florentw
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Registered: ‎11-09-2015

HI @hyungsoo1.kim 

There are multiple parameters to take in account. If you expend the AXI interconnect IP, you will see that it is composed from mutltiple sub-IPs and this configuration will change depending on the master and slave interfaces which are connected to it.

So you might want to give more details about the interfaces connected:

  • How many slaves/masters are connected?
  • Are multiples transactions happening between the slaves/master while you see this latency?
  • Are the slaves/master interfaces of the same standard (AXI3/AXI4/AXI4-Lite)?
  • Are they on the same clock?
  • How did you configure the AXI interconnect?
  • ...

You might want to provide the ILA or simulation for the latency you are seeing as well

There is no easy answer based on the description you are providing

PS: The PG059 has a latency section which is detailing the latency for the AXI interconnect. You might want to go through it


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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dgisselq
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Registered: ‎05-21-2015

The AXI specification has a rule that there be no combinatorial paths between inputs and outputs within either slaves or masters.

axi-spec-registered.png

Given that an interconnect is both an AXI slave and an AXI master, this means that you'll be stuck with a minimum of three clocks of latency:

1. One clock to accept the request from one of the interconnect's slave interfaces and to forward it to a slave
2. A second clock for the slave to process the request and return the result to the interconnect
3. A third clock to return the result to the master.

Sadly, if you want any kind of high speed operation, you'll need to pipeline some of the logic within the interconnect as well. As an example, in this open source design, two other clocks are used to ...

4. Decode the address to reference the slave, and
5. Arbitrate among multiple masters attempting to reference the same slave.

As a result, this interconnect will return a minimum latency of 5 cycles.


axixbar-latency.png

Even that, however, isn't the full story. What happens when a master requests an operation from slave 1, slave 2, and then slave 1 again? The open source interconnect above will wait for slave 1's acknowledgment before it offers arbitration to access slave 2, and then again wait for slave 2's response.  This can add more latency to each of these additional requests, and this is only the *minimum* latency--assuming all of the xREADY lines are high other than AxREADY.

axixbarx2-latency.png

(Note: Despite my best attempts to redraw these "to-scale" to match a trace, it looks like there are still some subtle errors within these--for example, ARVALID should be *low* following a reset, and the latency should start counting from the time ARVALID is first high, etc.)

Xilinx's interconnect supports several modes. One is a single-address, single data mode where all of the slave address lines, read and write, are shared.  This is meant for low-logic  implementations. The problem with this mode is that it turns an N:M interconnect into an N:1:M interconnect. Well, even that's not quite right, since this simplified mode merges read and write channels together. Hence N masters might have N read channels and N write channels, and connect to M slaves with M read and M write channels. In order to be able to share address and data lines across all channels, this becomes more of a (2N):1:(2M) interconnect where only one master will ever get access to any slave at a time. All other masters must wait.

AXI also supports a second interconnect methodology whereby the interconnect routes requests to slaves, and then arbitrates and routes those requests back to the master. Xilinx's interconnect also supports this mode in it's full N:M read and N:M write crossbar configuration. This isn't the panacea that it sounds like, however, since you can't route a packet with a given AXI ID to slave one, and then a second packet with the same AXI ID to slave two, only to have the second slave respond first. I haven't tested to see how Xilinx's interconnect prevents this from happening--but suffice to say that this operation would of necessity create even more latency.

It's worse than that even. Because any return routing algorithm based upon AXI IDs of necessity would create back pressure in the slave, as in dropping the RREADY or BREADY signals for slaves that haven't won arbitration, slaves that haven't been tested against backpressure might now fail and lock the bus up hard for the rest of the connected designs. Classic examples are the IP Packager designs (both the demonstration AXI and AXI-lite slaves) and even the AXI ethernet lite designs--both of which will drop returns (and lock your design) in the presence of any backpressure.

Dan

hyungsoo1.kim
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Registered: ‎03-24-2019

Thank  you for your replay and I'm answering your questions.

  • How many slaves/masters are connected?
    • slave 1ea / Master 2ea
  • Are multiples transactions happening between the slaves/master while you see this latency?
    • No. I sent 1ea read request to Master #1, did't send reqeust to Master #2 ( we connected two master, but only sent 1 read rqeust)
  • Are the slaves/master interfaces of the same standard (AXI3/AXI4/AXI4-Lite)?
    • yes AXI4
  • Are they on the same clock?
    • yes same clock
  • How did you configure the AXI interconnect?
    • Default mode. I didn't modify AXI interconnector configure

 

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florentw
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Registered: ‎11-09-2015

HI @hyungsoo1.kim 

Do you have an ILA capture or simulation waveform showing the latency?


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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hyungsoo1.kim
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Registered: ‎03-24-2019

Hi

 

Yes I have Simulation wave form. But I can't load wave form img file because of our company security policy.

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florentw
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Registered: ‎11-09-2015

Hi @hyungsoo1.kim 

Well... this will be hard to give much more advise if we do not know exactly what is happening.

I would have checked on the tready signals on the slave side (i.e. Master interface of the interconnect) to make sure this is not a backpressur from the downstream IPs

And also if there is a delay between the address and the data for write transaction which can be improved on the upstream IPs


Florent
Product Application Engineer - Xilinx Technical Support EMEA
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hyungsoo1.kim
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Registered: ‎03-24-2019

Thank you for your replay

 

I can send our waveform and simulation enviroment for receving your inform.

Could you give me your email? (as alrealy I iform, I can't attach our data because of our security poicy, but I can send email to you )

Thanks!

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