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vishy
Observer
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Registered: ‎09-22-2020

[AXI Interrupt Controller IP][Unable to generate software interrupts]

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Vivado: 2020.1
Board: Zynq Ultrascale+ (ZCU106)
IP: AXI Interrupt Controller

I have instantiate AXI Interrupt Controller IP in my Vivado Block Design like this:

scr1.png

 

scr2.png

 

I am controlling the AXI INTC IP with some AXI Master Lite agent to write to the internal AXI INTC IP registers. I am driving the hardware interrupt port (intr[0:0]) to 0 because I want to generate interrupts by writing to the internal IP registers, and not by driving the intr[0:0] port. For that purpose, I have enabled 2 software interrupts in the "Advanced" tab of the IP customization window.

My design goal:

Write to ISR register of the AXI INTC IP to trigger LEVEL (high) interrupt on irq port of the AXI INTC IP. So, for example, writing 0x2 to the Interrupt Enable Register (IER) and then writing 0x2 to ISR register should drive irq line to HIGH until the Interrupt Acknowledge Register (IAR) is cleared.

My problem: I

I have set up ILA to observer the AXI traffic and irq line when writing to the internal AXI INTC IP registers. This is a set of actions through which I try to achieve my design goal:

1.) Write 0x00000002 to the AXI adress with an offset 0x00000008 (IER) to enable Software Interrupt number 2: (note: axi_intc address is at 0x80000000)

scr4.png

 (NOTE: Is it normal that the AWADDR is set to 0x8000000C, which is the beginning of the next word, instead of 0x00000008?)


2.) Write 0x00000002 to the AXI adress with an offset 0x00000000 (ISR) to trigger the interrupt:

scr9.png

 

 

 


3.) Observe irq line and wait for it to become high. Check the Interrupt Pending Register (IPR on address with an offset 0x00000004) to see if the interrupt is pending.

scr8.png

 

As you can see, irq line is at no point changing its value from 0 to 1. However, Interrupt Pending Register (IEP) is indicating that there is an interrupt pending.

Is there something I am missing? Why is this simple procedure not working properly?

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adem369
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Registered: ‎02-18-2019

Did you correctly set Master Enable Register (MER)?

"The ISR register bits up to Number of Peripheral Interrupts is writable by software until the Hardware Interrupt Enable (HIE) bit in the MER has been set."

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adem369
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Contributor
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Registered: ‎02-18-2019

Did you correctly set Master Enable Register (MER)?

"The ISR register bits up to Number of Peripheral Interrupts is writable by software until the Hardware Interrupt Enable (HIE) bit in the MER has been set."

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vishy
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Registered: ‎09-22-2020
Master Enable Register: The least significant bit contains the Master Enable (ME) bit and the next bit contains the Hardware Interrupt Enable (HIE) bit. Writing a 1 to the ME bit enables the Irq output signal. Writing a 0 to the ME bit disables the Irq output, effectively masking all interrupt inputs.

Somehow, I have completely missed the point on writing 1 to the ME bit enables the Irq output. The HIE bit was written correctly to 0, but I needed to write 1 to ME bit in MER. Thank you.
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