Vivado: 2020.1
Board: Zynq Ultrascale+ (ZCU106)
IP: AXI Interrupt Controller
I have instantiate AXI Interrupt Controller IP in my Vivado Block Design like this:
I am controlling the AXI INTC IP with some AXI Master Lite agent to write to the internal AXI INTC IP registers. I am driving the hardware interrupt port (intr[0:0]) to 0 because I want to generate interrupts by writing to the internal IP registers, and not by driving the intr[0:0] port. For that purpose, I have enabled 2 software interrupts in the "Advanced" tab of the IP customization window.
My design goal:
Write to ISR register of the AXI INTC IP to trigger LEVEL (high) interrupt on irq port of the AXI INTC IP. So, for example, writing 0x2 to the Interrupt Enable Register (IER) and then writing 0x2 to ISR register should drive irq line to HIGH until the Interrupt Acknowledge Register (IAR) is cleared.
My problem: I
I have set up ILA to observer the AXI traffic and irq line when writing to the internal AXI INTC IP registers. This is a set of actions through which I try to achieve my design goal:
1.) Write 0x00000002 to the AXI adress with an offset 0x00000008 (IER) to enable Software Interrupt number 2: (note: axi_intc address is at 0x80000000)
(NOTE: Is it normal that the AWADDR is set to 0x8000000C, which is the beginning of the next word, instead of 0x00000008?)
2.) Write 0x00000002 to the AXI adress with an offset 0x00000000 (ISR) to trigger the interrupt:
3.) Observe irq line and wait for it to become high. Check the Interrupt Pending Register (IPR on address with an offset 0x00000004) to see if the interrupt is pending.
As you can see, irq line is at no point changing its value from 0 to 1. However, Interrupt Pending Register (IEP) is indicating that there is an interrupt pending.
Is there something I am missing? Why is this simple procedure not working properly?
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