08-11-2020 06:07 AM
I am using the Interconnect IP 1.7 (from IP catalog). We havent yet migrated to using the IP integrater version as we really do not want a wrapper IP file simply for the interconnect.
It appears that the WDATA channel WREADY is valid for only the first clock of a burst before de-asserting wready until AWADDR arrives. In our system it can take 6 clocks to generate AWADDR, which can have some severe knock ons elsewhere as the bandwidth is basically full and can cause buffer overflows.
Can we configure this interconnect to accept WDATA bursts without AWADDR (as allowed by AXI)? Or would we have to move to interconnect 2.1 in the IP integrator? Or do I just need to put a small buffer infront of WDATA to mitigate the turnaround?
08-11-2020 08:07 AM
An interconnect cannot act on W* channel information without knowing to which slave it is being addressed. This behavior is not therefore unexpected. There are even more reasons why the W* channel might be stalled as well--such as too many packets already being currently processed. If such a delay is undesired, it would make sense to place a buffer on the W* channel. One common such buffer is an AXI slice. Xilinx offers AXI slices for this purpose which might suit your need quite well.
08-11-2020 09:01 AM
@dgisselqWhile that is true, there is nothing stopping it buffering the wdata bursts and waiting for an AWADDR, as in AXI4 there are no out of order AWADDR/WDATA processing.
Our workaround for this will be to put a small FIFO (as a single slice isnt enough) on the WDATA line.
10-15-2020 10:15 AM
10-15-2020 03:31 PM
That is a rather unhelpful reply. Does 2.1 do what Im asking for? buffering of WDATA bursts before AWADDR arrives?
Also, the AR does NOT explain how to use Interconnect without IPI. It just says that you you can instantiate the crossbar in an empty IPI design, but that still requies you to use, and maintain, and IPI wrapper (which I would rather not do if I dont have to).