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shaikon
Voyager
Voyager
1,850 Views
Registered: ‎04-12-2012

AXI Lite Register Array

Hello,

In my code, I have an AXI Lite interface that should control MANY registers.

I know that in Vivado's IP catalog there's a component named "AXI GPIO" that accepts an AXI Lite bus and outputs wires. But what if I need a 100 of these ?

 

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18 Replies
katsuki
Xilinx Employee
Xilinx Employee
1,763 Views
Registered: ‎11-05-2019

Hi @shaikon 

It is recommended to create it as a custom IP.
For creating a custom IP, you can refer to UG1118, UG1119.

Thank you
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shaikon
Voyager
Voyager
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Registered: ‎04-12-2012

A register array that talks AXI LITE...this is such a ubiquitous block for almost any design.
Seems practical for Xilinx to have it as part of the IP catalog.
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dpaul24
Scholar
Scholar
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Registered: ‎08-07-2014

@shaikon ,

AXI4Lite isn't difficult and complicated.

Write an RTL myself that will R/W to a bunch of registers and keep it for in-house use for future projects.

I do it for our projects.

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richardhead
Scholar
Scholar
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Registered: ‎08-01-2012

This is something Ive never seen available in a catalogue, and something Ive seen done in many different ways at different companies.

At current company we have a generic VHDL 2008 block where I can provide a record type and a mapping functions as a generic and it will connect all the registers for you. You can even mask off all the registers you dont need to exist, so they just get synthesised away. It works in vivado 2019.2 and beyond.

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ami.kum
Adventurer
Adventurer
1,687 Views
Registered: ‎11-08-2018

Would it be possible for you to provide the RTL you have written for the registers. I have a design where i need to have multiple R/W registers which need to be accessed thru PCIe endpoint using the AXI-Lite Master interface.

 

Thanks

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shaikon
Voyager
Voyager
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Registered: ‎04-12-2012

I know it's not difficult. I also wrote a VHDL 2008 generic AXI Lite slave that works fine.

But many times when I work for different customers I get asked to add little custom user code as possible and use vends IPs as much as I can.

 

Now, Vivado does have a GPIO AXI LITE slave IP. It should be very easy to extend it to an array and make it a part of the IP Catalog

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ami.kum
Adventurer
Adventurer
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Registered: ‎11-08-2018

There is an option in Vivado Tool > Create and package new IP.

I can create a AXI4 peripheral with 100 registers. The issue is unlike AXI_GPIO which brings out the gpio port, the AXI4 peripheral does not.

It is not clear to me how user logic in FPGA to read/write to these 100 registers. Reading and Writing from Host via PCI is okay and there is no issue with it.

Using AXI_GPIO means I have to have 100 of these AXI_GPIO and that could blow up the size of axi_smartconnect. There must be an efficient way of doing what I am trying to achieve. I just need to understand how I can read/write to these registers from the user logic.

Please see the attached picture of my implementation

Untitled.png
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patocarr
Teacher
Teacher
1,661 Views
Registered: ‎01-28-2008

Hi,

  Probably the easiest way to have an AXI slave with a number of R/W registers is to use the "Create and package new IP"  menu item under Tools, and once the code is generated, edit it at will.

Screenshot 2020-10-01-10_37_14-Create and Package New IP_01.png

 The generated code is highly commented which makes its modification trivial. As a starting point for a generic parametrizable module, it doesn't get much simpler than this.

 

Thanks,

-Pat

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ami.kum
Adventurer
Adventurer
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Registered: ‎11-08-2018

Hi!

 

I create a user logic and added the ports. But I still don't see those ports on the top level of the IP created.

Please see the attached file.

maybe i am missing something.

All I want is those registers in the AXI peripheral to be available for internal user logic read and write when they are not being accessed by PCIE interface.

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patocarr
Teacher
Teacher
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Registered: ‎01-28-2008

Hi @ami.kum 

  Another approach would be to implement an AXI Master that takes instructions from the logic outside the block design, and connects to a new AXI Slave in the SMC interconnect, as shown in the diagram. These instructions can access any of the AXI slave devices depending on the memory range being hit. In this case, your slave IP wouldn't need any additional user ports.

Untitled.png

Thanks,

-Pat

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@shaikon ,

I think you are struggling with this problem because you are using Vivado's board design methodology beyond it's strength.  Pushing 100 registers out to various outputs, and then trying to mouse-connect them would be (IMHO) a nightmare.

Why not just create an AXI-lite module with the address space you need, fix the module (Xilinx's auto-created code will hang your design), and then keep the registers you set together with the logic that needs them within that design?

For reference, though, here's an example AXI-lite design that demonstrates using 32 registers.  It's a simple modification of this basic (working, not broken) AXI-lite design built to measure AXI (not lite) performance..

Dan

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shaikon
Voyager
Voyager
1,475 Views
Registered: ‎04-12-2012

It seems like you haven't read my previous message.

I'm not struggling with anything. I designed a generic AXI Lite slave a long time ago. It can accept as many registers as I desire just by setting the correct parameter.

But many times - I get asked to add as little custom as possible and instead use vendor IPs as much as I can.

So it would be nice if Xilinx had such an IP in there catalog - as it's very commonly required in designs.

Kind of like a FIFO - sure I can design my own...but why would I ? The IP catalog has one. I expect it to be the same way with the AXI slave register array...

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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015


But many times - I get asked to add as little custom as possible and instead use vendor IPs as much as I can.

So it would be nice if Xilinx had such an IP in there catalog - as it's very commonly required in designs.

Kind of like a FIFO - sure I can design my own...but why would I ? The IP catalog has one. I expect it to be the same way with the AXI slave register array...


Why would you?

  • There are bugs in Xilinx's IPs.  The most classic is in their demo AXI cores from which they encourage people to build their own designs, but there are bugs in their other cores as well (S2MM DMA, Ethernet-Lite, etc.).  If you build your own, you can at least control the time and schedule of when those bugs are fixed.  You can also make sure your own designs are formally verified, so they won't suffer from the bugs Xilinx hasn't yet managed to chase down. (Hint: They aren't formally verifying their own designs, neither will they release many of their proprietary components so they can be formally verified.)
  • How significant are these bugs?  They'll only cause the entire AXI bus to seize, locking up the rest of the design.
  • If you build your own, you can often increase the performance.  Many Xilinx bus components arbitrarily throttle the speed of the bus.  You can build your own against a more exactly standard. (100% throughput)
  • If you build your own, you can then switch to other FPGA vendors with less hassle.
  • If you build your own, you can import your design into an ASIC design without paying exhorbitant fees.

There are plenty of good reasons.

Dan

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richardhead
Scholar
Scholar
1,455 Views
Registered: ‎08-01-2012

@dgisselq 

For most companies, they do not have the time or resources to generate thier own axi infrastructure, let alone use formal methods, which is alien to most. And apart from the FOSS Yosys, the paid for formal tools are VERY expensive. Many companies wont use FOSS. So the Xilinx toolset is all they have. A reg file is something that might be missing from the toolset.

For larger companies, maintaining their own axi infrastructure can become worthwhile for the reasons you mention.

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ami.kum
Adventurer
Adventurer
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Registered: ‎11-08-2018

I do have a follow-up question. In the block digram, I have the PCIe connected to the DDR4 memory controller which connects to external DDR4 component.

What would be your recommendation, the path from PCIe to DDR4 read and write is handled. How can I access the DDR4 memory from my user logic. Do you suggest creating another AXI Master module to connect the internal User Logic to access the DDR4 memory space?

If yes, then I will have 3 AXI master - One PCIe endpoint, One to access the 100 registers, and the third one to access the DDR4 memory.

What is your recommendation on how to handle this? Only one AXI master can be active at any given time to avoid bus contention. How do I achieve that?

 

 

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richardhead
Scholar
Scholar
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Registered: ‎08-01-2012

For this, you would put an AXI interconnect - this allows N master to M slave connections. For example we have a design that has 6 Masters connected to a single DDR slave. The interconnect uses extra ID bits to differentiate between the masters.

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ami.kum
Adventurer
Adventurer
1,258 Views
Registered: ‎11-08-2018

Can you please provide the example design.

The ID bits you mentioned are they part of AXI interconnect interface. I will also check on the AXI interconnect interface.

Thanks for the insight.

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katsuki
Xilinx Employee
Xilinx Employee
867 Views
Registered: ‎11-05-2019

Hi @shaikon 

Did you resolve the first your post? You've probably seen posts from many members. It's a good idea to sort out the situation and post again.

Thank you.
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