cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
bafatsit
Visitor
Visitor
3,912 Views
Registered: ‎09-06-2016

AXI Ports, general question

Jump to solution

Hello,

 

I have a general questions about AXI on Zynq.

Please correct me if I'm wrong.

 

Zynq provides three AXI interfaces for the PS-PL interconnection. They are AXI_GP, AXI_HP, and AXI_APU.

All of them are of the type AXI-full, aren't they? (I couldn't find this info anywhere).

Now, I can't connect an AXI-Lite directly to the AXI_GP, because AXI_GP only implements AXI-full.

So I need the AXI_Interconnect to connect to the AXI_GP with AXI-full, but connects to my pcore with AXI-Lite.

 

Everything correct?

 

 

0 Kudos
Reply
1 Solution

Accepted Solutions
hpoetzl
Voyager
Voyager
5,605 Views
Registered: ‎06-24-2013

Hey @bafatsit,

 

Zynq provides three AXI interfaces for the PS-PL interconnection.

They are AXI_GP, AXI_HP, and AXI_APU.

It's a little bit more complicated than this ... in the Zynq, there are

  • Two 32bit General Purpose AXI Slave Ports
  • Four 32/64bit High Performance AXI Slave Ports
  • One 64bit AXI ACP Port
  • Two 32bit General Purpose AXI Master Ports

All of them are of the type AXI-full, aren't they?

Well, let's put it this way, they implement most parts of the AXI3 specification which is definitely more than AXI-Lite

 

I need the AXI_Interconnect to connect to the AXI_GP ...

The AXI Interconnect does all kinds of mapping between AXI slaves and AXI masters across versions (AXI 4 vs AXI 3) and capabilities (Full vs Lite).

 

Note that you need a master port to connect a slave to, and a slave port if you have an AXI master implemented in PL.

 

Hope this clarifies,

Herbert

-------------- Yes, I do this for fun!

View solution in original post

0 Kudos
Reply
5 Replies
dpaul24
Scholar
Scholar
3,903 Views
Registered: ‎08-07-2014

I can only comment on the following:

Now, I can't connect an AXI-Lite directly to the AXI_GP, because AXI_GP only implements AXI-full.

 

An AXI-full can be connected to an AXI-Lite.

Just drive 0's (or 1's, whatever is the protocol default) for the non-existing inputs and keep the non-existing outputs unconnected.

------------FPGA enthusiast------------
Consider giving "Kudos" if you like my answer. Please mark my post "Accept as solution" if my answer has solved your problem

0 Kudos
Reply
hpoetzl
Voyager
Voyager
5,606 Views
Registered: ‎06-24-2013

Hey @bafatsit,

 

Zynq provides three AXI interfaces for the PS-PL interconnection.

They are AXI_GP, AXI_HP, and AXI_APU.

It's a little bit more complicated than this ... in the Zynq, there are

  • Two 32bit General Purpose AXI Slave Ports
  • Four 32/64bit High Performance AXI Slave Ports
  • One 64bit AXI ACP Port
  • Two 32bit General Purpose AXI Master Ports

All of them are of the type AXI-full, aren't they?

Well, let's put it this way, they implement most parts of the AXI3 specification which is definitely more than AXI-Lite

 

I need the AXI_Interconnect to connect to the AXI_GP ...

The AXI Interconnect does all kinds of mapping between AXI slaves and AXI masters across versions (AXI 4 vs AXI 3) and capabilities (Full vs Lite).

 

Note that you need a master port to connect a slave to, and a slave port if you have an AXI master implemented in PL.

 

Hope this clarifies,

Herbert

-------------- Yes, I do this for fun!

View solution in original post

0 Kudos
Reply
florentw
Moderator
Moderator
3,886 Views
Registered: ‎11-09-2015

Hi @bafatsit,

 

The AXI interfaces on zynq are AXI3-full interfaces while Xilinx IPs have AXI4 interfaces. This will be the main reason why you cannot connect directly to an IP.

 

Then you might also need an Smart connect (replacing the AXI Interconnect IP) if you want to switch between an AXI4-full interface to an AXI4-Lite interface or if you need several slaves/master on the same interface.

 

Regards,

 

Florent


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
0 Kudos
Reply
bafatsit
Visitor
Visitor
3,855 Views
Registered: ‎09-06-2016

Ok, thanks.

Actually, I need to docu and cite this for university.

I need to reason why I chose AXI4-Lite.

 

So, where can I find the fact that AXI_GP is AXI3?

And is it possible to connect a AXI3 pcore to AXI_GP, or does Vivado prevent this?

Where would I find this info?

0 Kudos
Reply
florentw
Moderator
Moderator
3,852 Views
Registered: ‎11-09-2015

Hi @bafatsit,

 

I need to reason why I chose AXI4-Lite.

-> Most of the IPs are using AXI4. And AXI4-Lite is a simplified version of AXI4

 

So, where can I find the fact that AXI_GP is AXI3?

UG585:

zynq.PNG

 

And is it possible to connect a AXI3 pcore to AXI_GP, or does Vivado prevent this?

Yes it is possible. For example the VIP IP configured as AXI3 slave (it is just an example, there is no point of connecting a VIP to the zynq):

zynq2.PNG

 


Florent
Product Application Engineer - Xilinx Technical Support EMEA
**~ Don't forget to reply, give kudos, and accept as solution.~**
Tags (4)