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Registered: ‎10-07-2019

AXI QUAD SPI unreliable

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ALL

We have been working this for weeks, exhausted.  see similar here:

see older thread https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/Axi-Quad-SPI-fails-to-send-data-in-quad-mode-and-sends-it-in/m-p/839091

We are using Ultrascale, and AXI-QUAD-SPI, and StatupE3

We pull Data from AXI DDR4 controller with external DDR4 DRAM

External Micron 128Bb NOR

the program of the SPI Flash works 3 time ? 8 time ? but always fails at some point.

We see different commands simply 'missing' from the external SPI bus.

We are only using basic commands (we switched off from QUAD commands 6B/32), and now we use standard PAGE WRITE 0x02 !

The sequence now:

  1. READ FLAG Status 0x70 – until we get data 0x80
  2. Reset Enable FLASH 0x66
  3. WAIT min 40ns
  4. Reset Memory 0x99
  5. Wait for Reset to finish, 59us
  6. READ FLAG Status 0x70 – until we get data 0x80
  7. READ FLAG Status 0x70 – until we get data 0x80 (we don't need it twice)
  8. Write Enable 0x06
  9. READ Status 0x05 – until we get data 0x02 (for WEL)
  10. Bulk Erase 0xC7
  11. READ FLAG Status 0x70 – – data 0x00 for spec. 38s-114s, until it changes to – data 0x80 (we see 24-38s - varies depending on the sectors already erased.)
  12. Write Enable 0x06
  13. READ Status 0x05 – until we get data 0x02 (for WEL)
  14. PROGRAM 0x02 + 256B DATA = 40.9us per page of 256B
  15. READ FLAG Status 0x70 – until we get data 0x80 = 66 x FLAG READ of data 00 (Busy) until Rdy 80 = 138.67us (actual Flash Busy time)
  16. REPEAT at stage 12-15 till complete, up to 64K x 256B pages

 

So it works sometimes, and not others!

We have verified the Setup and hold on the flash is correct.

We believe its the AXI QUAD is simply getting confused ? not initialized correctly

We are using full AXI, 8bit, Enhanced mode, Performance mode, QUAD mode, Slave Micron, Clock 100MHz / 2 = 50Mhz, Slave = 1

 

We perform a reset of the AXI QUAD

and the sequence to below, as per PG153 PG 80 :

  1. TX_INIT
    1. Write SPICR, MASTER mode, CPOL+CPHA=00, Master-transaction = 0 (Inhibit)
    2. Clear IPISR (IRQ Status Reg)
    3. Disabling ALL Slave, all SPISSR register bits to 1 (AXI_QUAD thinks it’s a NEW COMMND)
    4. RESET SPI DTR and DRR FIFOs, writing into the SPICR register bits
    5. Set IPIER - enable Interrupts (TX empty, Command error)
  2.  WRITE command / data (WREN, BULK-ERASE, RST, RST-MEM, PROG):
  1. Load COMMAND  (+ ADDR + DATA) into SPIDTR
  2. SET SPISSR to set CS
  3. Write to the SPICR register to enable the master transaction inhibit bit
  4. Wait for IRQ

3. Check IPISR (IRQ Status Reg) :

IF IPISR= bit 13 {  // command error

     Call TX_INIT;

     back to ‘load command’ - If IPISR = bit 2 (DTR Empty) = success

} Else IF IPISR = bit 2 (DTR Empty) { // success

            Do next page

}

 

So above, all per the PG153 pg80 sequence.

We have tried 2x128B pages vs 1 x 256B pages.

CMD = 0x70 READ FLAG Status – until we get data 0x80 = usually approx 66 x FLAG READ of data 00 (Busy) until Rdy 80 = 138.67us (actual Flash Busy time)

 

So we don't know what is causing the SPI-QUAD to simply ignore commands?, when they are 'legal'

 

also, We see in PG153, the statements about Micron Flash, ONLY HOLD parts

We are using the MT25QU128ABA8ESF-0SIT , This support HOLD and RESET, are we OK ?

axi quad setup.JPEG
Example of page program.jpg
FLAG read after Page program.jpg
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Registered: ‎10-07-2019

Guys, We solved

works with internal or external STARTUPE3

in the end, our issue was clocking, and FF meta stable.

We found a flip-flop meta stability issue, from the NVME to the QUAD-SPI download, was causing a race-condition, due to time-delays (propagation) across the entire FPGA

This in turn was causing a download-go and a download-status to change ‘randomly’ and trigger a false done, and also cause stoppages part way through, missing sections like ERASE or PROG.

It wasn't the STARTUPE3 blocking, it was clocking and FF metastability on control signals with delays not bound.

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Registered: ‎01-22-2015

rob.walker@quantum.com 

I have not used the AXI Quad SPI IP.   However, I have seen many people on the Forum struggle to use it.

I get the impression that this IP complicates the relatively simple SPI communication interface.

It you don't get answers to your questions about the IP then you may want to code up your own SPI communication module.  The following posts may help you "roll your own".

https://forums.xilinx.com/t5/FPGA-Configuration/Qspi-flash-memory/m-p/1058871#M15397

https://forums.xilinx.com/t5/FPGA-Configuration/Qspi-Flash-memory/m-p/1061208#M15558

Cheers,
Mark

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Registered: ‎10-07-2019

see below for another example, here all the RST, RST MEM, C7 Bulk Erase all works fine, but the Program commands and program clock are all  mysteriously missing !!

missing program commands.JPG
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Registered: ‎10-07-2019
P.s this is now in STANDARD mode, from QUAD mode, as Standard mode does not check the command. I saw a few blogs saying try this so the command does not get ejected. but alas, here, AXI-QUAD is still doing its own thing even in Standard mode
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Registered: ‎10-07-2019

All, we think the issue is STARTUPE3 EOS signal.

It is supposed to be high after the Xilinx completes its load.  we check for High, then start our used of the SPI bus

But occasionally on the ILA, we have seen EOS go low - which would be why we are prevented from using the SPI bus (Why we see commands not present on the bus, even though AXI-QUAD thinks it sent them!)

Any ideas what would cause STARTUPE3 to re-initiate EOS low ? to take back SPI bus ?

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Registered: ‎10-07-2019

We removed the HWICAP module, and the problem with AXI-QUAD-SPI and access to STARTUPE3 pins (SPI Pins) was fixed, i.e the EOS signal behaves correctly

Hence we have a conflict when trying to instantiate all 3 modules, waiting Xilinx to educate us...

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Highlighted
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Registered: ‎10-07-2019

Guys, We solved

works with internal or external STARTUPE3

in the end, our issue was clocking, and FF meta stable.

We found a flip-flop meta stability issue, from the NVME to the QUAD-SPI download, was causing a race-condition, due to time-delays (propagation) across the entire FPGA

This in turn was causing a download-go and a download-status to change ‘randomly’ and trigger a false done, and also cause stoppages part way through, missing sections like ERASE or PROG.

It wasn't the STARTUPE3 blocking, it was clocking and FF metastability on control signals with delays not bound.

View solution in original post