04-20-2021 01:39 PM
I'm working with the AXI Quad SPI IP Core for the first time and was hoping to check whether my understanding of its limitations is accurate.
Some background: on the HW platform I'm working on, the target slave device is an Avalanche AS1016204-0108B0PWAR MRAM. As it is not any of the predefined "Slave Device" options, I've opted for "Mixed". The device is supposed to be capable of quad mode -- however, the command opcode that the manufacturer requires to access the appropriate configuration register (x87) is not recognized by the IP core, and throws a Command Error when I attempt to use it in my baremetal test app.
Based on this, and my review of PG 153, it is my understanding that only devices that share either the Winbond or the Micron command sets could potentially utilize quad mode with the AXI Quad SPI IP core, is that correct? It seems that quad mode is precluded otherwise (I'm thinking of Table 3-8 from PG 153 in particular, taking these "other" type of devices as functionally equivalent to "Mixed Mode Memories").
If there is something that I'm missing, or a way of expanding allowable command opcodes beyond what is listed in PG 153, I would really appreciate the guidance.
Thanks very much!
04-23-2021 04:20 AM
>> Your understanding is correct about the command support. The AXI Quad SPI core design is based on commands supported by standard SPI devices such as Winbond, Micron, Macronix, and Spansion memory only.
>> In "Mixed" mode, it selects a command subset in common with Winbond, Micron, and Spansion memory specifications.