cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Observer
Observer
423 Views
Registered: ‎04-06-2018

AXI Quad SPI IP ext_spi_clk

Jump to solution

The documentation appears to contradict a critical item.

The AXI Quad SPI v3.2 documentation PG153 (July 8, 2019) has a note to Table 1.1 that for Legacy and Enhanced core operation in Standard mode, Note 1:

"In this mode the ext_spi_clk can be the same as the axi_aclk or axi4_aclk, but it should not be less than the AXI CLK or AXI4 ACLK. This mode is specifically for slow operating devices that work on the SPI protocol. Examples of these devices are EEPROMs and SPI interface-based DACs."

Shouldn't the ext_spi_clk be the same OR less?  The performance metrics in another XAPP have AXI bus frequency of 100MHz and an ext_spi_freq of 50MHz in this mode.  That contradicts the note.  If the note is needed, the axi_aclk has to be the lame or lower than the "slow" ext_spi_clk to support those slow operating devices.  Table 2-1 is meaningless in "this mode."  This does not seem right.

If my slowest Legacy Standard SPI device takes 4MHz max SCLK and my system is configured for 100MHz AXI4-Lite, what should I do for axi_aclk versus ext_spi_clk?

Tags (2)
0 Kudos
Reply
1 Solution

Accepted Solutions
Xilinx Employee
Xilinx Employee
247 Views
Registered: ‎10-12-2018

Hi @johnhandwork,

Yes, you are correct. I have filed a change request (CR-1083027) with the factory against the performance documentation. It will be updated in next release.

Thanks & Regards
Anil B
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

4 Replies
Xilinx Employee
Xilinx Employee
370 Views
Registered: ‎10-12-2018

Hi @johnhandwork ,

The footnote under table 1-1 for specific configuration and the other footnote under table 2-1 for general use case.

If you are using Legacy Standard mode, the ext_spi_clk can be same as the axi_aclk or axi4_aclk, but it should not be less that the AXI CLK or AXI4 ACLK as mentioned in footnote-1 under table 1-1.

 

Thanks & Regards
Anil B
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
0 Kudos
Reply
Observer
Observer
356 Views
Registered: ‎04-06-2018

To be clear:

The AXI clock CANNOT be faster than the ext_spi_clk?

Please note the performance chart at https://www.xilinx.com/support/documentation/ip_documentation/ru/axi-quad-spi.html shows C_SPI_MODE 0 with ext_spi_clk=50 and s_axi4_clk=100.

According to the note 1, this is explicitly not appropriate.

0 Kudos
Reply
Observer
Observer
278 Views
Registered: ‎04-06-2018

Hi @abommera,

You attempted to interpret the note on the table for me.  I saw the note as inconsistent with its purpose and with other external data provided by Xilinx engineers, which is why I posted here.

I was hoping to get clarification on whether the note was inverted from its purpose, that the ext_spi_clk should not be more than the axi4_aclk to support slower SPI devices.  This inverted interpretation would be consistent with the tables showing higher axi4_aclk values than ext_spi_clk values and external performance data found in other documents.

I'd love some expert clarification on a point that appears upside down.

- John

0 Kudos
Reply
Xilinx Employee
Xilinx Employee
248 Views
Registered: ‎10-12-2018

Hi @johnhandwork,

Yes, you are correct. I have filed a change request (CR-1083027) with the factory against the performance documentation. It will be updated in next release.

Thanks & Regards
Anil B
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post