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deepdesign
Visitor
Visitor
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Registered: ‎08-23-2020

AXI Quad SPI Slave(Interrupt) Mode Problem

Hello,

I am using a Zynq-7000 SoC device. I want to design an SPI slave node using AXI Quad SPI IP Core. There is an external master device and its clock is 1.041 MHz. I am using xspi_slave_intr_example.c ( https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/spi/examples/xspi_slave_intr_example.c ) without using Interrupt Controller IP. Interrupt from AXI Quad SPI is directly connected to the ZYNQ Processing System. Therefore, the code is changed a bit to use XScuGic.

Axi Quad SPI IP Core is used in Standard Mode with 16 bytes FIFO Depth. Frequency Ratio is 16. S_axi_aclk is 100 MHz. ext_spi_clk is 33.312 MHz. Vivado version is 2018.2.

The problem is that the AXI Quad SPI core sends the correct data only in the first transaction. In other words, I've recognized that the transfer can't be done at the end of the first transaction. For example, the WriteBuffer is {80,81,82,83}. In Debug mode, MISO pin of SPI core sends as {80,81,82,83},{83,83,83,83},{83,83,83,83}...

The last data 83 repeats infinitely. XSpi_Transfer function is used in an infinite while loop. After sending the correct data {80,81,82,83}, in the second while loop, XSpi_Transfer function's status returns 21 which means the ip core is busy. Although the transfer is complete, the XSpi_Transfer function returns 21 since the ip core sends 83 infinitely.

How can I solve this problem? I want to do data transfer continuously with changeable data. 

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venui
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Moderator
443 Views
Registered: ‎04-09-2019

Hi Can you please check that the data which you are writing to the TXFIFO every time is getting updated properly or not.

I am suspecting that the loop which you are using in not updating data properly, i can check and let you know please attach source code.

Regards,

Venu

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