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jkrshnv
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Registered: ‎04-22-2015

AXI Quad SPI - master and salve interfacing

Hi

 

I need to interface 2 or 3 SPI slaves to an FPGA- most likely I will select Kintex device for this. Whatever data read from the SPI slaves have to be read by a microcontroller, based on interrupts. I guess the Microcontroller also should use an SPI  to FPGA, so that I need an SPI slave also on the FPGA.

 

1. Is this - having two Quad SPI devices on the FPGA - a good solution ?

2. Since I do not have a micrcontroller on the FPGA , can I put wrapper logic to interface with AXI4 side of the SPI cores , to do the programming of registers ?  From the WP417, figure 1, it looks like this is OK, is that right ?

3. My application is Industrial Control, so I am a bit worried about Microcontroller SPI to FPGA latency? Is there another way to do this, like having a dual port RAM on the FPGA read/written by Microcontroller ?

 

Thanks

Jayakrishnan. V

 

 

 

 

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