11-26-2018 07:30 AM - edited 11-27-2018 05:35 AM
I am trying to stream data from an ADC to DDR using Simple DMA. For that purpose I took a counter to test the connection and see if packets are missing. The counter is sending the data to a axis_data_fifo, which is connected to the DMA via AXI Stream. I set up the DMA with direct register mode in interrupt mode with a burst size of 256 (I also set tlast to 256 inside the counter ip) and 32 bit address width. When I dump the data written to DDR I can see that a lot of packets are missing, e.g. after packet 4612 (picture 5), 46149, 89963, 133779, ... If I plot the dumped data from DDR in octave I can see the lost packets appear to get lost on regular intervals (picture 8)
If I change the size of the FIFO it only changes the location of the missing packets. I already experimented with synchronous and asynchronous clocks for the FIFO.
My guess is packets get lost, because DMA takes too long after each write to DDR to recover and read the next burst from the FIFO, which can be seen on the screenshot, where DMA takes at least 7000 cycles until the next write to DDR (picture 4).
Has anyone a clue how to fix this?
12-18-2018 01:04 PM
Is your AXIS Data FIFO configured for "Packet Mode"? If so, shut that off; you want data to be able to pass through that front-end FIFO as soon as possible.
If your SW can't service the OTS DMA quickly enough, you might have to write your own custom module that has fixed addresses and requires no SW support while running. That's what I'm doing now--to get streaming ADC data across a PCIe link.