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riacho
Observer
Observer
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Registered: ‎12-03-2018

AXI S2MM does not work

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Hello,

What I am trying to do is get a image of sensor (OV7670) and send by DMA to DDR... the steps I followed were these:

Create project -> Language VHDL -> Create Block -> Add Zynq7 System -> Some settings in Customize Block Zynq and OK...

Add AXI Direct Memory Access -> in the Customize of IP DMA I only left checked: Enable Write Channel -> OK.

In Vivado -> Tools-> Create and Package New IP -> Create a new AXI4 -> Configurations: Stream - Master - 32 bits -> Edit IP -> Finish.

I understand that the code generated by Vivado 2018.2 do the stream a sequence of numbers from 1 to 8, like: 0x01, 0x02, 0x03 ... 0x08, in the read_pointer of eighth number tvalid comes down and tlast is generated.  The original code doesn’t work, so I realized this line:

-- Example design FIFO read pointer
signal read_pointer: integer range 0 to bit_num-1;

The bit_num its a return of function log2 of numbers outputs, in this case = log2(8) = 3, we have: 

-- Example design FIFO read pointer
signal read_pointer : integer range 0 to 3 -1;

Why? after that I changed to:

-- Example design FIFO read pointer
signal read_pointer : integer range 0 to 8;

And all run OK. Is this an error in the generated code by Vivado?

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vortex1601
Explorer
Explorer
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Registered: ‎12-11-2017

I had a lot of trouble using this block in a fall-through mode. It is very picky about the packet count.

I finally abandoned it and I wrote my own AXIMM to AXI-S bridge. This not only did the function that I wanted, but I could customize it with other blocks to fit my needs exactly: FIFOs, clock boundary crossing, width conversion, etc.

Using this bridge approach greatly simplified my AXI-S interaction with DMA. I can do scatter-gather DMA, use flow control, etc... not possible if the driver had to intervene every time and set up the packet count in a register like you have to with the AXIMM to AXIS IP block.

A clarification: I am referring to PG080, the "AXI4 Stream FIFO" IP block.

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riacho
Observer
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Registered: ‎12-03-2018

 

Yes, actually the error exists in generating the code by Vivado.

https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Master-Stream-custom-IP-Problem/td-p/654022

 

 

 

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vortex1601
Explorer
Explorer
1,255 Views
Registered: ‎12-11-2017

I had a lot of trouble using this block in a fall-through mode. It is very picky about the packet count.

I finally abandoned it and I wrote my own AXIMM to AXI-S bridge. This not only did the function that I wanted, but I could customize it with other blocks to fit my needs exactly: FIFOs, clock boundary crossing, width conversion, etc.

Using this bridge approach greatly simplified my AXI-S interaction with DMA. I can do scatter-gather DMA, use flow control, etc... not possible if the driver had to intervene every time and set up the packet count in a register like you have to with the AXIMM to AXIS IP block.

A clarification: I am referring to PG080, the "AXI4 Stream FIFO" IP block.

View solution in original post

mckinjo4
Explorer
Explorer
1,180 Views
Registered: ‎05-22-2008

It sounds like you are having problems with the the example code that vivado generates for AXI-Stream master/slave. That code is garbage. I ran across the below page:

http://que.no/index.php/2016/03/30/creating-axi4-stream-ip-xilinx-vivado/

And I found that the example it provides to work very well. I acutally use it as the basis for AXIS interfaces between several custom IP's, a Xilinx xfft9.0, and on both ends to interface to the AXI-DMA core in my design.