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rudy
Explorer
Explorer
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Registered: ‎04-29-2010

AXI SmartConnect multiple Slaves

I am trying to connect two AXI masters to a two SI ports on AXI SmartConnect, and then connect it to the processor. 

I have a simple block diagram like this:

rudy_0-1604014084663.png

I am reading "pg247-smartconnect.pdf", but not sure I understand how this is done?

According to the user guide, AXI ID signals cannot be used to identify the original master of a transaction. Instead, Xilinx recommends using the aruser and awuser signals to convey master identification information.

Is there any example design how to do this? I need the processor to know which master has sent the data. What is the best way of handling this? 

I have also noticed that lot of the time, I get warning messages when connecting smartConnect to the Processor. Something like this:

WARNING: [BD 41-237] Bus Interface property AWUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_HPC0_FPD(1) and /axi_smc/M00_AXI(0)
WARNING: [BD 41-237] Bus Interface property ARUSER_WIDTH does not match between /zynq_ultra_ps_e_0/S_AXI_HPC0_FPD(1) and /axi_smc/M00_AXI(0)

It seems like there is some warnings regarding aruser and awuser signals. How do we identify different masters by SmartConnect?  

 

 

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