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bruce_karaffa
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Registered: ‎06-21-2017

AXI Stream Breakout

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I have an RTL block with an AXI stream output running to a FIFO in my block design.  I would like to also run the tvalid signal to a pin so that I can monitor the transfer on a scope.  Expanding the AXI Stream port from the RTL and connecting the tvalid to my pin, I get this message:

 

WARNING: [BD 41-1306] The connection to interface pin /ObfuscatedName/CompFIFO_tvalid is being overridden by the user. This pin will not be connected as a part of interface connection CompFIFO

 

Why?  It's just a connection in FPGA fabric and can easily be run to two places.  Is there another way to do this in the block design?  I can add another port to my RTL and break it out in there, but it seems a silly way to do this.  The signal is already at the level that I want to look at it, but I can't get to it and leave it functional.

 

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tedbooth
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Registered: ‎03-28-2016

It's not ideal, but you should be able to expand the AXI Stream ports on your RTL block and the FIFO in block design.  From there you can directly connect all of the exposed pins between the RTL block and the FIFO and then also connect the tvalid to the pin.

 

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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tedbooth
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Registered: ‎03-28-2016

It's not ideal, but you should be able to expand the AXI Stream ports on your RTL block and the FIFO in block design.  From there you can directly connect all of the exposed pins between the RTL block and the FIFO and then also connect the tvalid to the pin.

 

Ted Booth | Tech. Lead FPGA Design Engineer | DesignLinx Solutions
https://www.designlinxhs.com

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bruce_karaffa
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Registered: ‎06-21-2017

It works, but it makes the block diagram ugly (uglier), so I have to agree it's not ideal.  Thank you for getting me through my Monday morning frustration.

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mmatusov
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Registered: ‎02-17-2009

@bruce_karaffa wrote:

It works, but it makes the block diagram ugly (uglier), so I have to agree it's not ideal.  Thank you for getting me through my Monday morning frustration.


Could you please explain what you did differently compared to when you got the error? I am facing exactly the same problem and I don't understand the solution. I was going to create a custom core for that but it seems like a huge overkill and waste of time. Thank you.

 

Never mind, I have found the answer record explaining this better: https://www.xilinx.com/support/answers/65254.html

My problem was that I was trying to break out from an external port. However, it doesn't seem to be possible to expand an external port, so I had to insert an interconnect block in the path.

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sandeep3003
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Registered: ‎07-14-2018

i have designed 8051 ip core and added the 8051 ip core in BD design interfacing with gpio ip it is generating warning message BD41-1306. can ypu help me out

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johnmcd
Xilinx Employee
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Registered: ‎02-01-2008

Use the System ILA. It supports 'interfaces' which can be set to axis rtl. Then you just connect the interface to your axis and you will be able to see all of the signals within the interface bundle.

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