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Adventurer
Adventurer
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Registered: ‎03-17-2017

AXI Stream Packing/Merging

I have a 128-bit AXI Stream with TKEEP. Most of my data transfers are full transfers, meaning that TKEEP is all 1's 0xFFFF. However, sometimes there can be a sparse transfer where some bytes are valid and others are null, meaning TKEEP might be 0x00FF. The bytes that are valid are always contiguous and begin by the LSB of the data. I need to pack/merge these sparse transfers so that all the transfers are always full transfers until the last transfer where it is allowable in association with a TLAST.

The AXI spec defines merging as "Merging is the process of combining bytes from two different transfers into one transfer. Merging can take place when a transfer has null bytes that can be removed, allowing later data or position bytes to be included. Merging can take place in association with packing."

The AXI spec defines packing as "Packing is the process of removing null bytes from a stream. Packing generally takes place in association with some other activity such as upsizing, downsizing, or merging. A data stream that uses TKEEP associations can be packed, by the removal of null bytes, to provide a more compressed data stream."

Is there a Xilinx IP that achieves this? If not, does anyone have an example of how to do this operation efficiently?

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Adventurer
Adventurer
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Registered: ‎04-04-2018

Re: AXI Stream Packing/Merging

I do not think there is a Xilinx IP for this, though I could be wrong. It sounds like all Xilinx IP are designed to only sample/use TKEEP bits when TLAST is set.

https://www.xilinx.com/support/documentation/ip_documentation/axi_ref_guide/latest/ug1037-vivado-axi-reference-guide.pdf#page=90.

You will probably need to write a custom module. I am not familiar with it, but I think there is a DATA_PACK HLS function:

Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com
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Adventurer
Adventurer
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Registered: ‎03-17-2017

Re: AXI Stream Packing/Merging

That was my finding so far as well. I don't utilize HLS, but I'm curious what that function does. Getting the pack and merge algorithm correct can be kind of tricky I think, depending how capable it needs to be, probably part of why Xilinx has avoided it, but there is certainly value in being able to do this operation.

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