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Visitor
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Registered: ‎05-21-2018

AXI Stream Switch Behavior

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I have a weird trouble with the AXI stream switch.

I have three AXI-stream FIFOs that feed a switch in a 3:1 configuration. The output then goes to an MCDMA.

Slot 0: Switch output
Slots 1-3: Switch inputs.

I see the data from the first FIFO transmit correctly, and then the second, but all the while the third FIFO is getting this every-other cycle TREADY that messes up the FIFO output. It never actually gets transmitted through the switch.

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Visitor
Visitor
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Registered: ‎05-21-2018

I believe I found a solution.

Each stream has a TDEST fixed: 00, 01 and 10

I had set the switch to use values 0x00000000 for TDEST low and 0x00001111 for TDEST high.

Changing to 0x0000FFFF for TDEST high has resulted in expected functionality.

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Visitor
Visitor
122 Views
Registered: ‎05-21-2018

I believe I found a solution.

Each stream has a TDEST fixed: 00, 01 and 10

I had set the switch to use values 0x00000000 for TDEST low and 0x00001111 for TDEST high.

Changing to 0x0000FFFF for TDEST high has resulted in expected functionality.

View solution in original post

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