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heyneman
Visitor
Visitor
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Registered: ‎08-16-2020

AXI Timer PWM: 100% duty cycle

I'm using an AXI timer with the XTmrCtr driver to create a PWM output and have run into an unexpected behavior.

When trying to set 100% duty cycle the output is held low rather than high. I've stepped through and verified that the period and high time are both being set the the same value (correct for my desired PWM frequency). I've looked through all the documentation I can find and I don't see any mention of this being a limitation (compared to e.g. being unable to set 0% duty cycle because the high time is 1 cycle + the load register value).

Has anyone used the AXI Timer PWM mode to generate 100% duty cycle successfully, or run into this same issue? Or can anyone point me to documentation discussing it?

Thanks,

-Barrett

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venui
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Registered: ‎04-09-2019

Hi,

As per my knowledge duty cycle means x% of low and Y% of high time should be equal to 100% of the clock cycle.

If you keep either X or Y as a 100% do you think it is a complete clock cycle(Tlow + Thigh = T).

If you would like to achieve low time as 100% and high time as 0% you can directly drive (Low)Zero over the line. 

If you would like to achieve High time as 100% and low time as 0% you can directly drive (High)One over the line.

So i think if you are using one of parameter(Low or High) as 100% no need of PWM, because either of the parameters should be(<100%)

Regards,

Venu 

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heyneman
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Registered: ‎08-16-2020

Thanks for the response Venu.

Yes, in my mind 100% DC is driving the line high, however if that DC is going to vary during operation (say to drive a motor, control brightness on an LED, etc) then it appears I cannot use the TmrCtr PWM mode and achieve 100% DC.

I basically did what you suggested for 0% DC; disabling the module drives the output low. But, it seems that in order to work around the 100% DC case I would need to add additional logic in the PL to drive the output port from a logic high signal rather than the output of the TmrCtr block.

Have you seen the behavior I've described, or confirmed that that the IP block does or does not support 100% duty cycle?

-Barrett

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