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Registered: ‎02-03-2019

AXI - UART 16550

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Can anybody please tell why block_value numbers 95,103,111 and so on assigning to lcr[3:0],I got the logic about (characters and stop bits),but i am not getting why the numbers 95,103 etc assigning.

https://opencores.org/websvn/filedetails?repname=uart16550&path=%2Fuart16550%2Ftrunk%2Frtl%2Fverilog%2Fuart_regs.v

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Moderator
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Registered: ‎01-09-2019

Hello shivunp8@gmail.com 

I just looked through the code you linked, but this is my interpretation.

It seems that those values are just the decimal value that would create a delay of a certain number of clock cycles.  If you look a few lines after those are defined it says that "on the posedge of the clock, if a write happened on the fifo, we will set that block_value to block_cnt".  Then for the next several clock cycles, the block_cnt is decremented until block_cnt is equal to all 0's.  The thre_set_en can be brought high because there is no 1's in the value for block_cnt.

Basically this entire logic is a delay function with variable delay depending on how the design was setup (if you have 2 stop bits you need more delay, and if you have 7 bits for each word that will take more delay than 5, but less than 8).  You can see these delays as comments in the switch-case statement for lcr (the value in the comments directly relates to the values in the Table 2-11 in PG143).

Thanks,

Caleb

Thanks,
Caleb
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Moderator
Moderator
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Registered: ‎01-09-2019

Hello shivunp8@gmail.com 

I just looked through the code you linked, but this is my interpretation.

It seems that those values are just the decimal value that would create a delay of a certain number of clock cycles.  If you look a few lines after those are defined it says that "on the posedge of the clock, if a write happened on the fifo, we will set that block_value to block_cnt".  Then for the next several clock cycles, the block_cnt is decremented until block_cnt is equal to all 0's.  The thre_set_en can be brought high because there is no 1's in the value for block_cnt.

Basically this entire logic is a delay function with variable delay depending on how the design was setup (if you have 2 stop bits you need more delay, and if you have 7 bits for each word that will take more delay than 5, but less than 8).  You can see these delays as comments in the switch-case statement for lcr (the value in the comments directly relates to the values in the Table 2-11 in PG143).

Thanks,

Caleb

Thanks,
Caleb
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Scholar
Scholar
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Registered: ‎05-21-2015

Do be aware that there are some serious flaws within that core, flaws that might even cause it to transmit something you didn't intend to transmit.

Just sayin,

Dan

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