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fpga_newbs
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Newbie
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Registered: ‎10-08-2020

AXI USB 2.0 Device

Hi all,

I'm trying to put together some design requirements for a system that samples 32 ADCs to gather 24MB of total data per second.

This data is required for transmission over a USB 2.0 interface and I've identified the AXI USB 2.0 Device as a potential solution.

If anyone has experience using this core, or just know your way around a user guide, could you please help me with the following:

  1. Does this sound like something that could be implemented onto a mid-range Artix-7? (Cost is an important factor in this design)
  2. Does 24MBps of payload data sound realistic for this core/device pairing?
  3. What design advice do you have to help ensure this data rate could be reached, e.g. efficient use of the endpoints, using DMA etc.

Many thanks!

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