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Observer
676 Views
Registered: ‎02-04-2020

## AXI Understanding: AXI_AWDDR/ARDDR

Hello Community,

i have a understanding Problem with the AXI.

I have an IP with this Adress (0x9005 0000 to 0x9005 0FFF) RANGE (4k) than i send a messages over microblaze to my ip.

What is my AWADDR for the first and secound burst? What kind of Value has AWADDR?.

Is it like:

1. Send_data==> 10 times 32 Bits for first Burst==>  AWADDR = 0x0000.

2. Send_data==> 10 times 32 Bits for next Burst==> AWADDR = 0x0004.

3. Send_data==> 10 times 32 Bits for next Burst==> AWADDR = 0x0008.

4. Send_data==> 10 times 32 Bits for next Burst==> AWADDR = 0x000C.

Is that correct? if not which value going to have AWADDR? And how can i calculate this Value?

best regards

jeko

Tags (2)
1 Solution

Accepted Solutions
Scholar
568 Views
Registered: ‎05-21-2015

Okay, let's start at the top.  AWADDR and ARADDR come from, in your case, the Microblaze CPU.  The values are set by your C code.  Therefore, you can write something like:

``````char *ptr = (char *)0x090050000;

for(int k=0; k<20; k++)
*ptr++ = (char)k;``````

In this case, AWADDR will start at 32'h90050000 and it will increment from 32'h90050000 to ..001, ..002, ..003, ..004, all the way up to ..014 (i.e. 20 in decimal).

``````int *iptr = 0x90050000;

for(int k=0; k<20; k++)
*iptr++ = k;``````

Then the CPU would have issued addresses 0x90050000, ..004, ..008, ..00c, ..010, ..014, etc. all the way up to ..00050 (i.e. a 20*4=80 decimal, but written in hex).

While CPU's can issue burst requests, they don't typically do so for PL memory mapped addresses--simply because such addresses so often don't contain *memory*.  This forces the CPU to (most often) issue singleton requests where AWLEN and/or ARLEN are equal to zero.  Yes, you will get faster performance if you let these AxLEN values be much larger, but CPU's don't typically have instructions to read or write more than one item at a time.  For this reason, you'll find the AWLEN and ARLEN values equal to zero.  (Some CPU's might use an AxLEN value of 1 for unaligned accesses--but I'm not sure how the Microblaze CPU handles unaligned addressing.)

Burst addressing, with AxLEN larger than one, comes into play in one of two scenarios.  1) When the CPU cache is reading (or sometimes writing) a whole cache line, or 2) if you have a hardware bus master such as a DMA that is issuing burst requests.  In such cases, AxADDR will be issued for the first value in the burst and then incremented according to the nature of the burst.

Note that the CPU doesn't know how to compose instructions into burst operations.  As it receives instructions from memory, it issues requests of the bus.

Dan

9 Replies
Scholar
656 Views
Registered: ‎08-01-2012

AXI Adressing is always meant as a byte address. So in a system that uses 32 bit DATA words, then each word is separated by 4 bytes - giving the sequence that is very common of 0x0 0x4 0x8 0xC.

Are you using full AXI4 or AXI4L ? What are you trying to access?

Observer
636 Views
Registered: ‎02-04-2020

Thank you.

I use a microblaze 32 bit and AXI lite. I try to send some data into my ip for calculation like: data1 + data2.

I just wanna understand how this awaddr going to set. And why 0x04 and then 0x08 ... Why not like 0x100 to 0x200?. Who is going to change the awaddr from 0x04 to 0x08?

0x04

recivedata = s_Axi_data(32bit);

0x08

recivedata2 == s_Axi_data(32bit);

...

Scholar
569 Views
Registered: ‎05-21-2015

Okay, let's start at the top.  AWADDR and ARADDR come from, in your case, the Microblaze CPU.  The values are set by your C code.  Therefore, you can write something like:

``````char *ptr = (char *)0x090050000;

for(int k=0; k<20; k++)
*ptr++ = (char)k;``````

In this case, AWADDR will start at 32'h90050000 and it will increment from 32'h90050000 to ..001, ..002, ..003, ..004, all the way up to ..014 (i.e. 20 in decimal).

``````int *iptr = 0x90050000;

for(int k=0; k<20; k++)
*iptr++ = k;``````

Then the CPU would have issued addresses 0x90050000, ..004, ..008, ..00c, ..010, ..014, etc. all the way up to ..00050 (i.e. a 20*4=80 decimal, but written in hex).

While CPU's can issue burst requests, they don't typically do so for PL memory mapped addresses--simply because such addresses so often don't contain *memory*.  This forces the CPU to (most often) issue singleton requests where AWLEN and/or ARLEN are equal to zero.  Yes, you will get faster performance if you let these AxLEN values be much larger, but CPU's don't typically have instructions to read or write more than one item at a time.  For this reason, you'll find the AWLEN and ARLEN values equal to zero.  (Some CPU's might use an AxLEN value of 1 for unaligned accesses--but I'm not sure how the Microblaze CPU handles unaligned addressing.)

Burst addressing, with AxLEN larger than one, comes into play in one of two scenarios.  1) When the CPU cache is reading (or sometimes writing) a whole cache line, or 2) if you have a hardware bus master such as a DMA that is issuing burst requests.  In such cases, AxADDR will be issued for the first value in the burst and then incremented according to the nature of the burst.

Note that the CPU doesn't know how to compose instructions into burst operations.  As it receives instructions from memory, it issues requests of the bus.

Dan

Mentor
457 Views
Registered: ‎06-10-2008

Good explanation for AXI full, but @jeko91 mentioned using AXI lite and then there is no burst support and thus no AxLEN and every access is a singleton request.

But your question does make me wonder if an AXI Interconnect or SmartConnect will mask off the most significant bits for you while it routes the AXI transactions. In other words, will your IP see AxADDR 0x00000000 or 0x90050000? It will definitely not see a 16 bit AxADDR like 0x0000 implies.

Observer
441 Views
Registered: ‎02-04-2020

hi Mentor,

I see with ILA AWADDR: 0x9005 0000 // then 0x9005 0004  // then 0x9005008 ....

( +0x0000 0004  all time why?).

I dont know how is the increment part going to work.

Why all time +0x04  // why not like:

0x9005 0000 // then 0x9005 1234  // then 0x9005 7463 ....

I wanna know why is this +4?

how can i set this 0x04 incrementel and how can i change this.

best regards

jeko

Mentor
418 Views
Registered: ‎06-10-2008

That is what Dan already explained perfectly. It depends on what your application is doing. What part of your microblaze code initiates the transaction? If there is no program, then there won't be any accesses.

Observer
414 Views
Registered: ‎02-04-2020

ok thank you.

its depend like int => 4 Byte then 0x9005 0000 // 0x9005 0004 // 0x9005 0008.

for char => each time +1. Thank you both.

best regards

Jeko

Scholar
405 Views
Registered: ‎05-21-2015

In many (all?) cases, Xilinx's AXI infrastructure will not mask off the top address bits.  I have no idea why not.  A slave with only 4 32b registers doesn't need to see any more than 6 address bits.  It's somewhat confusing for newbies, who then want to create bus errors if the top bits aren't correct somehow.

When building my own interconnects, I drop the extra address bits the first chance I get--otherwise you are just wasting logic for no useful gain.

Dan

Mentor
378 Views
Registered: ‎06-10-2008

That's odd. This means that every IP instance should either know its address for a full comparison or the size of its area in the memory map for masking. Sure, masking off is more optimal. But if there is no masking in the IP, then every instance needs to be configured differently with its base address. It makes me realize that AXI4 actually should have a variable width address bus that each interconnect can create based on the memory map.

Btw. Apologies for hijacking this thread.