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edoardo.cerini
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Registered: ‎05-08-2015

AXI VDMA strange behaviour tvalid and tready

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Hello everybody

 

I'm working very hard to use AXI VDMA but there's something I can't understand. the m_axis_mm2s_tvalid and the s_axis_s2mm_tready works totally random.

I'm using Vivado 2014.4 and VDMA v6.2. I'm implementing this on a zedboard.

 

This is my design:

VDMA4_design.jpg

 

I have 2 VDMAs, one for writing and another one for reading.

 

I use the Test Pattern Generator of xilinx to generate a tartan bars, and I connect it directly to the s_axis_s2mm of VDMA_0.

Then I created a controller for sending the output of the TPG (through th VDMAs) to a VGA screen.

The m_axis_mm2s of VDMA_1 is connected to my IP (the controller of VGA).

The VGA_ctrl sends the outputs to the screen and controls the stream of the data from VDMA_1 setting the tready to 1 only when it needs the data to send the data to the VGA screen..

 

The VGA_ctrl works perfectly if connected directly to the TPG, so there are not problem with it.

 

 

theese are the the configurations of the VDMAs

VDMA_reading_cfg.png

 

VDMA_writing_cfg.jpg

 

this is the addressing of the VDMAs and of the processor

VDMA_Addressing.jpg

 

 

this is what I wrote in the SDK. the size of the video is 1280x1024, so I counted 5120 of stride and hsize (1280*32/8). and 1024 for the vsize.

 

#include <xil_printf.h>
#include <xil_types.h>
#include <stdio.h>
#include "platform.h"
#include "xil_io.h"

int main()
{
		//S2MM config

	    Xil_Out32((0x43000000) + (0x30)  , 0x8B);		//S2MM_VDMACR : 8Bh

	    Xil_Out32((0x43000000) + (0xAC)  , 0x00100000);		//S2MM_START_ADDRESS of first frame: 0

	    Xil_Out32((0x43000000) + (0xA8)  , 0x00001400);		//S2MM_FRMDLY_STRIDE to 5120 byte per line

	    Xil_Out32((0x43000000) + (0xA4)  , 0x00001400);		//S2MM HSIZE: to 5120 bytes per line
	    Xil_Out32((0x43000000) + (0xA0)  , 0x00000400);		//S2MM VSIZE: 1024 lines

	    //MM2S config

	    Xil_Out32((0x43010000) + (0x00)  , 0x8B);		//MM2S_VDMACR: 8Bh

	    Xil_Out32((0x43010000) + (0x5C)  , 0x00100000);		//MM2S_Start_Address of first frame: 0

	    Xil_Out32((0x43010000) + (0x58)  , 0x00001400);		//MM2S_FRMDLY_STRIDE to 5120 byte per line

	    Xil_Out32((0x43010000) + (0x54)  , 0x00001400);		//MM2S HSIZE: 5120 bytes per line
	    Xil_Out32((0x43010000) + (0x50)  , 0x00000400);		//MM2S VSIZE: 1024


    return 0;
}

I use 1 frame buffer stored since he location 0x00100000 as I checked here:

VDMA_SDK_cfg.jpg

 

 

but in the end this is what I get for ILA core:

VDMA_tvalid.jpg

 

How can you see the axi_vdma_1_m_axis_mm2s_tvalid that should be always 1, goes between 1 and 0 totally random.

The same is for axi_vdma_0_m_axis_mm2s_tready.

This obviously stop the streaming and nothing works.

 

How is it possible that theese 2 signals of streaming change so randomly?

Could be a problem of the axi protocol which sees the channel busy and stop the streaming? 

I'm a newbie with FPGA and hardware world, so I can have done a very stupid mistake. please help me finding the problem.

 

Thanks in advance

 

Edoardo

 

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bwiec
Xilinx Employee
Xilinx Employee
15,621 Views
Registered: ‎08-02-2011

Hello Edoardo

 

i need to connect a camera instead of TPG in the future, by the way I really can't understand how can it be normal,because if tvalid or tready goes down the streaming will stop, so what is the VDMA for if not for streaming?

Oh I see, good point. The VDMA can be made to accept/send data in streaming fashion if everything is setup properly.

 

It sounds like possibly a bandwidth issue. Here's the settings I'd recommend to begin with:

- VDMA MM sides should be at least 64. Set them manually

- Set VDMA max burst length at least 16

- Make sure the VDMA MM clocks are at least as fast as the stream clocks.

- Set AXI Interconnect explicitly to use a crossbar width of 64 or greater

- Interconnect clocks should be at least as fast as VDMA MM clocks

- HP port clock should be at least as fast as VDMA MM clocks

 

Can you provide details of your clocking?

www.xilinx.com

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edoardo.cerini
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8,923 Views
Registered: ‎05-08-2015
sorry a mistake:

How can you see the axi_vdma_1_m_axis_mm2s_tvalid that should be always 1, goes between 1 and 0 totally random.
The same is for axi_vdma_0_m_axis_s2mm_tready.
This obviously stop the streaming and nothing works.
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bwiec
Xilinx Employee
Xilinx Employee
8,908 Views
Registered: ‎08-02-2011
Hello,

There's nothing inherently wrong with the fact that tvalid/tready toggle like this. It is completely legal per the spec. It may be a consequence of clock rates/data widths. What are you trying to accomplish?
www.xilinx.com
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edoardo.cerini
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Registered: ‎05-08-2015
Thank you for the answer.
i need to connect a camera instead of TPG in the future, by the way I really can't understand how can it be normal,because if tvalid or tready goes down the streaming will stop, so what is the VDMA for if not for streaming?
P.s. I noticed if I use only the mm2s VDMA, the tvalid is always 1. This happen only if I put only one VDMA in the design.
So I'm thinking it can be a problem of having 2 VDMA connected to the same Axi_mem_interconnection or to the same high performance port of the processor.

What can I do? Thanks in advance

Edoardo Cerini

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bwiec
Xilinx Employee
Xilinx Employee
15,622 Views
Registered: ‎08-02-2011

Hello Edoardo

 

i need to connect a camera instead of TPG in the future, by the way I really can't understand how can it be normal,because if tvalid or tready goes down the streaming will stop, so what is the VDMA for if not for streaming?

Oh I see, good point. The VDMA can be made to accept/send data in streaming fashion if everything is setup properly.

 

It sounds like possibly a bandwidth issue. Here's the settings I'd recommend to begin with:

- VDMA MM sides should be at least 64. Set them manually

- Set VDMA max burst length at least 16

- Make sure the VDMA MM clocks are at least as fast as the stream clocks.

- Set AXI Interconnect explicitly to use a crossbar width of 64 or greater

- Interconnect clocks should be at least as fast as VDMA MM clocks

- HP port clock should be at least as fast as VDMA MM clocks

 

Can you provide details of your clocking?

www.xilinx.com

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edoardo.cerini
Visitor
Visitor
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Registered: ‎05-08-2015
Thank you very much. it was a bandwidth issue. Now it's working perfectly with a 110 Mhz clock

Edoardo Cerini
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bwiec
Xilinx Employee
Xilinx Employee
8,850 Views
Registered: ‎08-02-2011
Great! Glad it's working okay now. Good luck with your design.

Brian
www.xilinx.com
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32100004
Observer
Observer
8,461 Views
Registered: ‎05-06-2015

Hello Edoardo

 

I'm a beginner and I'm also learing VDMA IP and trying to use it to transport Image data. I want to use your project as a tutorial because it shows the whole process in detail.

搜狗截图20150724152713.png

this is  made in vivado 2014.4 ,which just like yours. The xlconstants all set to high,and TPG sets like

搜狗截图20150724153041.png

And the Address map shows as below

搜狗截图20150724153606.png

and the SDK C code

#include <xil_printf.h>
#include <xil_types.h>
#include <stdio.h>
#include "platform.h"
#include "xil_io.h"

int main()
{
		//S2MM config
		//u32 temp;
		int i;

		init_platform();
		xil_printf("\r\n--- Entering main() --- \r\n");
	    xil_printf("0x00100000  %x\r\n",Xil_In32(0x00100000));
	    xil_printf("0x00000000  %x\r\n",Xil_In32(0x00000000));
	    Xil_Out32((0x43000000) + (0x30)  , 0x8B);		//S2MM_VDMACR : 8Bh

	    Xil_Out32((0x43000000) + (0xAC)  , 0x00100000);		//S2MM_START_ADDRESS of first frame: 0

	    Xil_Out32((0x43000000) + (0xA8)  , 0x00001400);		//S2MM_FRMDLY_STRIDE to 5120 byte per line

	    Xil_Out32((0x43000000) + (0xA4)  , 0x00001400);		//S2MM HSIZE: to 5120 bytes per line
	    Xil_Out32((0x43000000) + (0xA0)  , 0x00000400);		//S2MM VSIZE: 1024 lines


	    //MM2S config

	    Xil_Out32((0x43010000) + (0x00)  , 0x8B);		//MM2S_VDMACR: 8Bh

	    Xil_Out32((0x43010000) + (0x5C)  , 0x00100000);		//MM2S_Start_Address of first frame: 0

	    Xil_Out32((0x43010000) + (0x58)  , 0x00001400);		//MM2S_FRMDLY_STRIDE to 5120 byte per line

	    Xil_Out32((0x43010000) + (0x54)  , 0x00001400);		//MM2S HSIZE: 5120 bytes per line
	    Xil_Out32((0x43010000) + (0x50)  , 0x00000400);		//MM2S VSIZE: 1024

	    for(i=0;i<10000;i++);//delay

	    xil_printf("0x00100000  %x\r\n",Xil_In32(0x00100000));
	    xil_printf("0x00000000  %x\r\n",Xil_In32(0x00000000));
    return 0;
}

However, I cannot get the expected result. I think the number will change after DMA configuration, but it does not change.

original.jpg

 

I'm wondering where I was wrong. Could you help me point out my problems?

 

Best Regards,

   32100004

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