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Registered: ‎12-27-2012

AXI WLAST strange behaviour in Central DMA transfer

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Hi,

I am working with Central DMA from Xilinx and, during the transfer of 17 words of 32-bit, I noticed, during the simulation, that there are two bursts: one with 16 beats with size 32 bit, and another with 1 beat with size 32 bit.

Looking at the signals behaviours, I noticed that WLAST goes high in correspondance of the 16-th beat of the first burst (that is correct), and that it stucks at WLAST = 1 even if the burst ends and starts the second burst.

Please have a look at the simulation results, attached to this post. The WLAST signal is highlighted in purple. I wounder whether this should be the correct behaviour of the master CDMA.

Thank you for any support,

GiacomoScreenshot from 2019-08-29 14-17-57.png

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Scholar
Scholar
386 Views
Registered: ‎02-01-2013

 

The behavior is correct. The WLAST signals asserts during the last beat of an AXI transaction. As you've already noted, your overall data movement is broken down into 2 separate AXI transactions: a 16-beat, burst transaction and a single-beat, non-burst transaction. WLAST is asserted to signify the last beat/transfer of each of those transactions.

Note that WLAST is not valid unless an AXI "transfer" is occurring--which, by definition, is "only when both the VALID and READY signals are HIGH". The WLAST signal value is a don't-care when a transfer is not taking place. In this instance, the DMA IP knows that it has de-asserted WVALID at the end of the 16-beat burst, so it's free to do whatever it wants with WLAST--like leaving it high. When the next transfer starts (for the single-beat transaction), WLAST becomes/is-already valid.

Not unnecessarily de-asserting WLAST between the two transactions is the most efficient way to handle this situation.

-Joe G.

 

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Scholar
Scholar
387 Views
Registered: ‎02-01-2013

 

The behavior is correct. The WLAST signals asserts during the last beat of an AXI transaction. As you've already noted, your overall data movement is broken down into 2 separate AXI transactions: a 16-beat, burst transaction and a single-beat, non-burst transaction. WLAST is asserted to signify the last beat/transfer of each of those transactions.

Note that WLAST is not valid unless an AXI "transfer" is occurring--which, by definition, is "only when both the VALID and READY signals are HIGH". The WLAST signal value is a don't-care when a transfer is not taking place. In this instance, the DMA IP knows that it has de-asserted WVALID at the end of the 16-beat burst, so it's free to do whatever it wants with WLAST--like leaving it high. When the next transfer starts (for the single-beat transaction), WLAST becomes/is-already valid.

Not unnecessarily de-asserting WLAST between the two transactions is the most efficient way to handle this situation.

-Joe G.

 

View solution in original post

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Participant
Participant
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Registered: ‎12-27-2012

Thank you, now it is clear for me.

Giacomo V.

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