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user123random
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Registered: ‎05-02-2017

AXI burst read transaction returns unknown RDATA bits

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I have two AXI interfaces with two Xilinx AXI BRAM IPs and I am testing one of the AXI interfaces.

My AXI burst write transactions had zero AXI protocol violations.

However, during my data loopback test, Xilinx AXI BRAM IP slave returns me unknown RDATA highlighted in red colour in the simulation waveform for AXI burst read transaction after time=235ns

Any idea why ?

 

See AWADDR at t=60ns and WLAST at t=210ns

also ARADDR at t=235ns

do you guys notice anything wrong with the AXI waveform before t=235ns ?

BRESP also returns 0 which is okay at t=220ns

 

It is also not due to burst read during burst write dependency since I have already tried to increment AWADDR by a large constant larger than (AWLEN+1) * (1 << AWSIZE)

 

KnwxzWg

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user123random
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harikade
Xilinx Employee
Xilinx Employee
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Registered: ‎05-01-2019

Hi,

Can you provide complete design? I see below error during elaboration

Module <cache_controller> not found while processing module instance <nn_feature_cache>

Also, can you mention which vivado version is being used ?

 

Thanks,

Harika.

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user123random
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