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hsuh6
Visitor
Visitor
277 Views
Registered: ‎04-28-2020

AXI clock converter output is in high-z state.

Hi,

 

While I am working on the AXI clock converter, I found that the some outputs of the IP is not coming out properly right after the reset.

I am using two processor reset system to feed aresetn and aclk signals for two clock domains. For example,

processor_system_resest_0 gets the clock of 177MHz and peripheral_aresetn of this reset module is connected to the m_axi_aresetn port of the AXI clock converter

processor_system_resest_1 gets the clock of 266MHz and peripheral_aresetn of this reset module is connected to the s_axi_aresetn port of the AXI clock converter

 

I checked that both reset signals and that they are coming out correctly at the right timing.

AXI converter waveform.PNG

Is it because the m_axi_aresetn goes high after s_axi_aresetn is given? 

m_axi_rdata should be passed to the s_axi_rdata in the waveform. Instead, s_axi_rdata is just having a long high-z state.

What is the proper way of resetting this IP?

 

**below is added for a detailed description of the problem**

While I am writing this post, I got something

AXI converter bug.png

I think maybe the problem is AXI clock converter is not passing the data "00000000" to the other side properly (but it's my two cents. This may be the problem of reset.)

 

What I did wrong with AXI clock converter and why this data is not passed or not reset properly?

2 Replies
abouassi
Moderator
Moderator
135 Views
Registered: ‎03-25-2019

Hi @hsuh6,

Are you asserting the aresertn for a minimum of 16 clocks as recommended on PG059?

abouassi_0-1612464661230.png

 

Best regards,
Abdallah
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bruce_karaffa
Scholar
Scholar
131 Views
Registered: ‎06-21-2017

The red signals with xxxx are not high-Z, they are undefined.  Their state is unknown, not high-Z

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