01-08-2021 09:47 PM - edited 01-08-2021 09:50 PM
While I am working on the AXI clock converter, I found that the some outputs of the IP is not coming out properly right after the reset.
I am using two processor reset system to feed aresetn and aclk signals for two clock domains. For example,
processor_system_resest_0 gets the clock of 177MHz and peripheral_aresetn of this reset module is connected to the m_axi_aresetn port of the AXI clock converter
processor_system_resest_1 gets the clock of 266MHz and peripheral_aresetn of this reset module is connected to the s_axi_aresetn port of the AXI clock converter
I checked that both reset signals and that they are coming out correctly at the right timing.
Is it because the m_axi_aresetn goes high after s_axi_aresetn is given?
m_axi_rdata should be passed to the s_axi_rdata in the waveform. Instead, s_axi_rdata is just having a long high-z state.
What is the proper way of resetting this IP?
**below is added for a detailed description of the problem**
While I am writing this post, I got something
I think maybe the problem is AXI clock converter is not passing the data "00000000" to the other side properly (but it's my two cents. This may be the problem of reset.)
What I did wrong with AXI clock converter and why this data is not passed or not reset properly?
02-04-2021 10:51 AM