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Explorer
Explorer
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Registered: ‎09-25-2017

AXI clock converter vs AXI Interconnect

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Hi,

  Since AXI Interconnect already has the function to allow CDC between CPU's AXI Lite control bus to IP cores, why is there a need for AXI clock converter? 

  In Xilinx MIPI IP example, the design use a common clock to all Mxx_ACLK input to AXI Interconnect ( CPU AXI bus to control IP Cores).  Then it inserts AXI Clock Converters in the path of  a AXI bus to  some of the IP Cores for CDC purposes.  

  Why not just use a different clock at the Mxx_ACLK input of AXI Interconnect IP?

Neo

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Xilinx Employee
Xilinx Employee
913 Views
Registered: ‎03-30-2016

Hello wtneo@leica 

>All the designs I have seen uses AXI Interconnect to do CDC, there is no need to explicitly do this using AXI Clock Converter. 

Your understanding is correct that AXI Interconnect do CDC inside the IP.
You can use Slave/Master with different clock. No need to instance AXI clock converter outside.
-- If you are using asynchronous clock, you will find that AXI interconnect has AXI clock converter module inside the IP
    ( You can check by expand  the IP )

>So I am curious is there a reason to do this in this example.

I think this is to reduce the logic used in the Example. If you use synchronous Slave/Master clock, your AXI interconnect will not have AXI clock converter module inside.
As you can see that not all of the path need CDC. So I think the Example Design creator wants to specify which paths need Clock converter, and which paths don't.

Thanks & regards
Leo

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Observer
Observer
1,023 Views
Registered: ‎06-19-2019
can u add an image?
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Highlighted
Explorer
Explorer
999 Views
Registered: ‎09-25-2017

Hi,

  This is taken from MIPI CSI-2 RX Subsystem example for ZCU102 board.

  

  axi clock converter.PNG

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Observer
Observer
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Registered: ‎06-19-2019

the IC has one slave and many masters, if they r all working with the same clock domain then implementation of the AXI is very simple and with low latency and small amount of logic.

there is no prevention of using only one AXI IC with different clocks but it might be that in this way it was easier to close timing.

the clock converter serve as a buffer between the different clock domains, instead of having a common block between clock domain then there is a specific block for that and the implementation can create better separation between the clock domain.

it is very easy to check, remove the clock converter and connect directly to the AXI_IC and look on the reports.

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Explorer
Explorer
965 Views
Registered: ‎09-25-2017

Hi,

  All the designs I have seen uses AXI Interconnect to do CDC, there is no need to explicitly do this using AXI Clock Converter.  So I am curious is there a reason to do this in this example.

Neo

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Xilinx Employee
Xilinx Employee
914 Views
Registered: ‎03-30-2016

Hello wtneo@leica 

>All the designs I have seen uses AXI Interconnect to do CDC, there is no need to explicitly do this using AXI Clock Converter. 

Your understanding is correct that AXI Interconnect do CDC inside the IP.
You can use Slave/Master with different clock. No need to instance AXI clock converter outside.
-- If you are using asynchronous clock, you will find that AXI interconnect has AXI clock converter module inside the IP
    ( You can check by expand  the IP )

>So I am curious is there a reason to do this in this example.

I think this is to reduce the logic used in the Example. If you use synchronous Slave/Master clock, your AXI interconnect will not have AXI clock converter module inside.
As you can see that not all of the path need CDC. So I think the Example Design creator wants to specify which paths need Clock converter, and which paths don't.

Thanks & regards
Leo

View solution in original post