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Registered: ‎09-10-2019

AXI interconnect Ultrascale+

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Hello,

I have i design with multiple clock domains. I have my custom IP (clkx1) clock , and  would like to interconnect it with PS via an AXI Interconnect IP. Should i connect all the clocks with my clkx1 (and the CDC is done inside the PS? ) or should i connect the slaves with ps clock?

Also, how should i connect the fpd_aclks

Below i have my already connected design (With yellow is my clkx1 domain and with green is ps clock). Is it something wrong? (In AXI interconnect  i have enabled CDC stages ).

AXI_interrconnect.PNG

Thanks ,

Theo

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Scholar
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Registered: ‎08-07-2014

@tkontogiorgis,

Ok, now I get it.

So at the end, is it only my choice what should i choose ( PS auto CDC or PL interconnect CDC ) ? Are there any advantages or disantvantages?

In my opinion PS auto CDC would be better because it is a hard-macro, already existing.

 

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Scholar
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Registered: ‎08-07-2014

@tkontogiorgis,

While configuring the AXI Interconnect IP cores, do you not get the option to configure the master and slave clocks as sync or async?

I see from the v2.1 docu - "Each of the SI and MI on the AXI Interconnect core has its own aclk pin, so that transfers through the Interconnect can cross clock domains. "

 

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Registered: ‎09-10-2019

Hello @dpaul24 ,

How can i achieve that? 

I read this post, https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/AXI-Interconnect-Clock-connexions-issues/td-p/795993 

and i am little confused. Do i need to set all the clocks as my clkx1 or not?

Thanks

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Registered: ‎08-07-2014

@tkontogiorgis,

The answers are in the thread link you have posted.

Should i connect all the clocks with my clkx1 (and the CDC is done inside the PS? ) or should i connect the slaves with ps clock?

No need to connect the slaves with PS clock as CDC is done inside the interconnect. You can keep the master and slave side clocks separate.

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Hello @dpaul24 ,

and thanks for the quick response. I am more confused now :). As far as i understand there are 2 options:

1) Connect in the PL interconnect IP the same clock (which will be the clock of my IP).

2) Connect in the PL interconnect IP different clocks (on the slave side ps clock and on the master side my IP clk).

1) Are the 2 options both correct?

2) In 2 case should i add CDC stages in the PL interconnect IP right?

3) Is there any difference between the 2 cases?

4) How do i set the fpd clocks in each case?

Sorry, but i am confused.  

"No need to connect the slaves with PS clock as CDC is done inside the interconnect" : Which interconnect? The PS interconnect?

"You can keep the master and slave side clocks separate" : If the CDC is done in the PS interconnect then why should i keep them separate? Having my IP's clock wouldn't be the correct solution?

Thanks,

Theo

 

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Registered: ‎08-07-2014

@tkontogiorgis,

See the AXI IC core has the following clk signals, ACLK, S*_ACLK and M*_ACLK.

Now if I refer to the AXI IC Product Guide v2.1, Chapter3, Clock Conversion:

Each of the SI and MI on the AXI Interconnect core has its own aclk pin, so that transfers through the Interconnect can cross clock domains. The AXI Crossbar core also has its own aclk input. When the clock source driving the aclk pin of a SI or MI is different than the clock source driving the internal Crossbar, an AXI Clock Converter core is automatically instantiated along the pathway.

So as I understand it, ACLK, S*_ACLK and M*_ACLK can all be different. Or ACLK = S*_ACLK or ACLK = M*_ACLK. It is up to the designer how to connect the clocks. If your design supports, then ACLK = S*_ACLK = M*_ACLK.  I think that answers <1>.

<2> The product guide says that the tool does the conversion for you inside the AXI IC core. Nothing to do yourself.

In the block diagram you have posted, it is the AXI Interconnect core, I am referring to.

Did you try running Connection Automation for the BD and see what happens?

 

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Registered: ‎09-10-2019

Hi @dpaul24 ,

I've just tried to make the automatic connection and the IP connected all the ports automatically. So in this case the tool automatically connected all the ports with clkx1.

So at the end, is it only my choice what should i choose ( PS auto CDC or PL interconnect CDC ) ? Are there any advantages or disantvantages?

Assuming that i have different clocks. Should i enable CDC stages and enable FIFO also or not?

Thanks again,

Sincerely

Theo

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Registered: ‎08-07-2014

@tkontogiorgis,

So at the end, is it only my choice what should i choose ( PS auto CDC or PL interconnect CDC ) ?

I do not understand what you mean by PS auto CDC.

 

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Hello @dpaul24 ,

I mean the Accepted as solution answer here : https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/AXI-Interconnect-Clock-connexions-issues/td-p/795993

The transition between the clock domains is done inside the PS (you don't see it in vivado)" .

 

Theo

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Registered: ‎08-07-2014

@tkontogiorgis,

Ok, now I get it.

So at the end, is it only my choice what should i choose ( PS auto CDC or PL interconnect CDC ) ? Are there any advantages or disantvantages?

In my opinion PS auto CDC would be better because it is a hard-macro, already existing.

 

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