cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
9,505 Views
Registered: ‎04-19-2014

AXI interconnect synchronous clock converter

Hello,

 

I'm struggling to figure out why I'm getting a timing violation on my AXI stream interconnect.

 

I have two clocks generated by the PS, a 10MHz clock and 100MHz clock. When I feed them into an AXI stream interconnect for my master and slave streams, Vivado auto generates a AXI stream clock converter. When I look at the properties that it gets assigned, it says the clocks are async, and that the clock ratio is 1:2. I would expect to see the clocks showing as sync and a ratio of 10:1.

 

When I run the synthesis and view the schematic, I can see there is indeed a FIFO that was generated to handle the async clock domain crossing. The AXIS clock converter states that it handles synchronous clock crossings without using a FIFO.

 

This ultimately leads to a timing violation on the reset signal. I'm really not sure how else to track this down and fix it.

 

I also tried using only a single "Processor System Reset Module" with the slowst_sync_clock connected to FCLK_CLK1 (10MHz) like the PG164 says but that caused timing violations all over the board.

 

It looks to me like the two clocks generates by the PS are not getting treated as synchronous. Is there some setting I have missed somewhere?

 

Any advice would be appreciated.

 

Thanks!

Xilinx Dev-2014-12-16-19-52-35.png
Xilinx Dev-2014-12-16-19-51-44.png
Xilinx Dev-2014-12-16-19-53-35.png
Xilinx Dev-2014-12-16-19-53-42.png
Xilinx Dev-2014-12-16-20-00-02.png
Xilinx Dev-2014-12-16-20-03-49.png
0 Kudos
Reply
4 Replies
Highlighted
Scholar
Scholar
9,480 Views
Registered: ‎11-09-2013

where does it say that 1:10 sync clock crossing is handled without fifo?

 

if be surprised if it does that.

0 Kudos
Reply
Highlighted
Visitor
Visitor
9,472 Views
Registered: ‎04-19-2014

I assumed that while reading PG805.

 

Asynchronous clock rate conversion between the input and output uses an internal
FIFO Generator instantiated module.

 

But I might be mistaken. I can try and generate a stream clock converter module manually and see what the synthesizer output looks like.

 

Though I still have the feeling that I’m missing a timing constraint that says the 2 clocks are phase aligned.

 

0 Kudos
Reply
Highlighted
Scholar
Scholar
9,465 Views
Registered: ‎11-09-2013

async will use FIFO always

 

but the sync version may have to use FIFO as well depend the ratio

 

say you have 57:13 clock ratio? I do not see it possible that the sync version can always be implemented without fifo

0 Kudos
Reply
Highlighted
Visitor
Visitor
9,353 Views
Registered: ‎04-19-2014


@trenz-al wrote:

async will use FIFO always

 

but the sync version may have to use FIFO as well depend the ratio

 

say you have 57:13 clock ratio? I do not see it possible that the sync version can always be implemented without fifo


Correct. I'm using a 10MHz clock and 100MHz clock so a 1:10 ratio.

0 Kudos
Reply