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Registered: ‎07-27-2020

AXI to AXIS in the form of a FIFO for input to AEAD


I am trying to implement an already existing AEAD IP onto a Zynq SoC but am finding difficulty in using a FIFO to send some data as input to the AEAD. As the image below shows, I want to separate the public and secret data into the AEAD IP.


I am successfully using DMA to send the public data, however as I want to separate the two sources of input, I cannot use the same DMA to send the secret data. I considered using a second DMA IP for this, however due to the small amount of data being sent through this channel it seems overkill. Also, I wouldn't know what to connect to the S_AXIS_S2MM port of the second DMA IP as the output from the AEAD would be connected only to the S_AXIS_S2MM on the first DMA IP. 

Below is an image of what the block diagram should look like. My issue is with implementing the secret data input (SDI), specifically with the IP labelled AXI-Lite FIFO in this image. The closest IP I am able to find in the library is the AXI Data FIFO which does not provide the desired output (output is AXI whereas I want either AXIS or the FIFO output shown in the previous image). Do I have to create this as a custom IP?


I am new to development using Xilinx products so I apologise if my question is novice.

Thanks in advance.

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Registered: ‎06-30-2020

The AXI-Stream FIFO IP provides MM2S and S2MM interfaces. Alternatively, the FIFO Generator can give you a one directional stream interface, but you would need to do the MM2S conversion separately.

Less to the question, but an observation on your diagram, the logic on your SDI FIFO in the first diagram strike me as odd.

--From your diagram:
sdi_valid_in <= sdi_fifo_empty AND (NOT sdi_ready);
sdi_fifo_read <= NOT sdi_ready;

--What I believe you want:
sdi_fifo_read <= (NOT sdi_fifo_empty) AND sdi_ready;
sdi_valid_in <= sdi_fifo_read;

But the AXI interfaces around the FIFO should handle that for you.