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tedxg
Visitor
Visitor
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Registered: ‎07-17-2019

AXI width converter master has no IDs

Hi all,

I have a AXI IP chain as follows: PCIe master -> AXI data width converter -> AXI chip2chip in "master" mode. The protocol is AXI4.

The PCIe's AXI master and the width converter's AXI slave interfaces both have ID signals (ARID/AWID/RID/BID). However, the width converter's master interface and the chip2chip's slave interface do not have IDs. The IDs are important for my design so I need to keep them. Where are the IDs going?

Screenshot attached with part of my block diagram.

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Screenshot 2020-10-27 at 5.33.56 PM.png
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dgisselq
Scholar
Scholar
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Registered: ‎05-21-2015

@tedxg ,

AXI ID's don't make very good user signals.  They can be remapped by any AXI bridges, and the specification specifically recommends remapping them within interconnects.  As user signals, they aren't likely to be portable from one version of the AXI infrastructure that might just happen to treat them properly to another.

For example, it would be perfectly legal in this case for the width converter to remove downstream AXI ID's if it guaranteed proper ID processing from the perspective of the upstream master.

Dan

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tedxg
Visitor
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Registered: ‎07-17-2019

Hi Dan,

Thanks for your reply. I understand the limitations of using IDs for user signals but my design has a hard reliance on them, and in general this has worked very well for deployments in the past. We are switching to a new top-level interconnect topology, which is why the width converters are now necessary. Historically my design has benefited tremendously from separating requests by ID, since it allows downstream slave components to reorder responses between IDs, thereby improving performance.
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