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robin2121
Observer
Observer
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Registered: ‎07-03-2017

AXI4 DMA PL to AXI3 PS, ID issues

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Hi,

 

Here is my project :

 

I make a DMA from scratch in VHDL in a ZYNQ PL, which is compatible with AXI 4. It takes AXI 4 stream in input and output an AXI full interface connected to the PS of the Zynq device with HP0 slave port.

 

But I saw that the PS use AXI 3 protocol and AXI 3 have ID signals which are removed in AXI 4. So my AXI full interface have to be AXI 3.

 

In project examples, and in the documentation, Xilinx uses IP Interconnect to convert AXI 4 to AXI 3 to communicate with the PS, so it is the IP Interconnect which generates IDs signals. But I wouldn't like to use an Interconnect IP, it is a simple project with a single DMA master and the PS.

 

If I have understood :

AXI 4 can support 256 words in one burst and AXI 3 only 16, and IDs signals is useful to convert AXI4 256 words to an AXI3 16 words with threads or work in parallel with many masters and many slaves.

 

My question is : 

If i want to use a 16 words burst from the beginning, no threads, and I have only one master (DMA) and one slave (HP0) need I thoses signals ? Can I fixe it to any constant ? Or if not, what values can I fixe it ?

 

I read ARM and Xilinx documentation but did not understand very well thoses signals. Does anybody have a very simple concrete example for use IDs signals ?

 

Thanks for your time and your help. 

Robin

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kravi
Xilinx Employee
Xilinx Employee
3,018 Views
Registered: ‎02-26-2014

Hi,

 

The ID signal is used for tagging that particular transaction. When the master gets the response from the slave, slave sends back the same ID value on response channel (write response, read data). This is useful when master needs to differentiate the transactions.

For simple masters they can be tied to a constant value, may all '0's.

The behavior of ID is same in AXI3 and AXI4.

 

Regards,

Ravi

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smarell
Community Manager
Community Manager
2,025 Views
Registered: ‎07-23-2012
You need to have a protocol converter at least if not the whole AXI Interconnect. Is there a specific reason for not using DMAC or AXI DMA?
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robin2121
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Registered: ‎07-03-2017

I would like to understand how works the HP0 port (one reason is for a pedagogic goal) and I would like to optimize my DMA module and directly output an AXI3 interface which can connect HP0 without Interconnect IP or AXI converter IP (which are include in Interconnect).

 

I have only problems with ID signals of AXI3 interface, I have already done others signals interface.

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kravi
Xilinx Employee
Xilinx Employee
3,019 Views
Registered: ‎02-26-2014

Hi,

 

The ID signal is used for tagging that particular transaction. When the master gets the response from the slave, slave sends back the same ID value on response channel (write response, read data). This is useful when master needs to differentiate the transactions.

For simple masters they can be tied to a constant value, may all '0's.

The behavior of ID is same in AXI3 and AXI4.

 

Regards,

Ravi

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