Hi,
Here is my project :
I make a DMA from scratch in VHDL in a ZYNQ PL, which is compatible with AXI 4. It takes AXI 4 stream in input and output an AXI full interface connected to the PS of the Zynq device with HP0 slave port.
But I saw that the PS use AXI 3 protocol and AXI 3 have ID signals which are removed in AXI 4. So my AXI full interface have to be AXI 3.
In project examples, and in the documentation, Xilinx uses IP Interconnect to convert AXI 4 to AXI 3 to communicate with the PS, so it is the IP Interconnect which generates IDs signals. But I wouldn't like to use an Interconnect IP, it is a simple project with a single DMA master and the PS.
If I have understood :
AXI 4 can support 256 words in one burst and AXI 3 only 16, and IDs signals is useful to convert AXI4 256 words to an AXI3 16 words with threads or work in parallel with many masters and many slaves.
My question is :
If i want to use a 16 words burst from the beginning, no threads, and I have only one master (DMA) and one slave (HP0) need I thoses signals ? Can I fixe it to any constant ? Or if not, what values can I fixe it ?
I read ARM and Xilinx documentation but did not understand very well thoses signals. Does anybody have a very simple concrete example for use IDs signals ?
Thanks for your time and your help.
Robin
