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kevinevans
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Registered: ‎09-06-2018

AXI4 Lite read hangs, and RREADY is not deasserting after RVALID is toggled

I have a custom AXI4 Lite peripheral on a Zynq 7010 on a Microzed board. It's connected via an AXI interconnect (1 slave/11 master) interface. This peripheral is connected on the M11 port and I have other AXI4 Lite IPs that work just fine.

I'm trying to do a read from a register on the IP from the PS and it hangs any time I do a read: in Xilinx SDK, the debugger disconnects with "APB AP transaction error, DAP status f0000021" or it just sits on that line of code and does nothing. Using MRD in the XSCT console at that address returns "Memory read error at 0x43C60000. Timeout waiting for the Instruction Complete bit" and it hangs. What's interesting is that writes to that address work just fine, it's just reads that cause it to crash.

I've attached an ILA to the AXI signals and it looks completely normal, except `RREADY` is not being deasserted by the AXI subsystem:

Capture.PNG

Here's the code that I'm running to do the write and read:

	uint32_t* base = (uint32_t *)0x43c60000; // address given to it via the Address Editor
	*base = 0x1;                             // works just fine
	xil_printf("reg0 = %x\n", *base);        // causes PS to hang

 

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jg_bds
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Registered: ‎02-01-2013

 

The transaction in the ILA clip looks appropriate. The problem is likely in the PS configuration.

Please post your block diagram and memory address map.

-Joe G.

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kevinevans
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Registered: ‎09-06-2018

Here's the block diagram and address map screenshots, with the IP marked in red.

 

bd.pngaddresses.png

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dgisselq
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Registered: ‎05-21-2015

@kevinevans,

Would you like to share your code?  It might be that the bug takes place before the trace.  It should be possible to figure that out from your code.

You should also be aware that there are bugs in the IP Packager's example/demo AXI-lite core.

Dan

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jg_bds
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Registered: ‎02-01-2013

 

Did you use the Xilinx template to create your AXI slave IP?

Can you expand the S_AXI port on your IP, and make sure you don't have any signals that might make Vivado think it's a regular AXI, instead of an AXI-Lite--like ID signals?

Can you also instrument the M_AXI_GP0 interface of the PS, so we can see transactions simultaneously on that interface (interconnect slave side) and M10_AXI?

-Joe G.

 

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